In the past decades, device scaling along the Moore's Law
trajectory has been the major focus of technology innovation in
the semiconductor industry. However, this scaling has in recent
years slowed down due to power limits, lithography complexity,
and other physics limitations. The semiconductor industry has
identified several looming technology challenges and expected
new design paradigms that demand new "design-based equivalent
scaling" approaches to enable continuation of Moore's Law. This
thesis addresses several aspects of these challenges, for both
the "More-Moore" and "More-than-Moore" domains.
Interconnect reliability increases the design uncertainty in
advanced node technologies. Electromigration is a growing
concern in sub-22nm technology. To close a costly "chicken-egg"
loop that spans library characterization and signoff in the
presence of design adaptivity, we study the interlock among
front-end (device) aging, voltage scaling, and
electromigration; we furthermore quantify timing and power
costs of meeting lifetime requirements. Based on this, we
provide new signoff guidelines and demonstrate that suboptimal
choice of voltage step size and scheduling strategy can result
in decreased product lifetime.
As semiconductor technology advances, leading-edge product
companies must rapidly improve yield for designs that seek to
reach mass production while still early in the adoption of a
new technology node. We study the possible mitigation of yield
loss by opportunistic, last-stage redundant logic insertion in
early advanced-node production. We describe a yield estimation
methodology, and propose an integer linear programming-based
optimization of redundant logic insertion for opportunistic
yield optimization.
In sub-14nm processes, routability challenges arise from
multiple patterning and pin access constraints that drastically
weaken the correlation between global-route congestion and
detailed-routing design rule violations. We present a method
that applies machine learning techniques to effectively predict
detailed-routing design rule violations after global routing,
as well as detailed placement techniques to effectively reduce
detailed-routing design rule violations.
Beyond conventional design paradigms, three-dimensional
integrated circuits (3DICs) with multiple tiers are expected to
achieve large benefits (e.g., in terms of power and area) as
compared to conventional two-dimensional designs. However,
upper bounds on the potential power and area benefits from 3DIC
integration with multiple tiers are not well-explored. We use
the concept of implementation with infinite dimension to
estimate upper bounds on power and area benefits achievable by
3DICs versus 2DICs. We observe that design power sensitivity to
implementation with different dimensions correlates well with
placement-based Rent parameter of the netlist. We show that the
quality of netlist synthesis and optimization benefits from
awareness of the target implementation dimension (e.g., 2D
versus 3D).
Last, aggressive requirements for low power and high
performance in VLSI designs have led to increased interest in
non-conventional computation paradigms. Approximate and
stochastic hardware can achieve improved energy efficiency
compared to accurate, traditional hardware modules. To exploit
any benefits of approximate and stochastic hardware modules,
design tools should be able to quickly and accurately estimate
the output quality of composed approximate designs. We propose
new accuracy estimation methodologies for approximate hardware
and stochastic hardware, respectively. For stochastic circuits,
we further investigate opportunities to optimize circuits under
aggressive voltage scaling. We find that logical and physical
design techniques can be combined to significantly expand the
already powerful accuracy-energy tradeoff possibilities of
stochastic circuits.
