Donald Bren School of Information and Computer Sciences

When synthesizing a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operation into control steps. Prior to scheduling, most existing behavioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators used in the design be specified in multiples of a clock cycle. A bad choice of the clock cycle could adversely affect the performance of the synthesized design. We present mathematical proofs of setting clock cycle length with zero clock slack and an algorithm for estimating the system clock based on a clock slack minimization criteria. This algorithm guarantee the minimum average clock slack.