UC San Diego

In the late CMOS era, integrated-circuit physical design and signoff face three major challenges – (i) complex operating conditions, (ii) low-power demand, and (iii) growing design margin. Future scaling of designs and the continuation of Moore’s Law itself require better physical design optimization and signoff methodologies. Toward this end, this thesis presents novel optimization techniques and signoff methodologies to respectively address these challenges in three main thrusts.

In modern SoC implementations, multi-mode design is commonly used to achieve better

circuit performance and power across voltage scaling, “turbo” and other operating modes. Furthermore, PVT variations result in a large number of corners for circuit design and signoff. To mitigate the impact of complex operating conditions and corner explosion, in the multi-mode multi-corner optimization thrust, this thesis presents approaches to optimize signoff corner selection, reduce skew variation in clock network, and perform scan timing optimization without causing any QoR degradation in functional mode.

Energy and battery lifetime constraints induce new and critical challenges to IC designs, especially for mobile and “Internet of Things” (IoT) applications. To achieve power autonomy in the era of a slowing Moore’s law, low-power techniques must be exploited. To minimize design power and energy, in the low-power optimization thrust, this thesis presents a stacked power domain scheme to align SoC power domain voltages with battery voltages for power delivery efficiency and battery lifetime improvements, a novel flop tray generation technique for clock power reduction, and a low-cost resilient design flow to enable better than worst-case design for energy savings.

The 2013 ITRS update of system driver models reveal a “scaling gap” since 2008. One

root cause of the density scaling slowdown is the growing design margins due to variability, reliability, etc. To reduce the design margins and to pursue design-based equivalent scaling, in the mixed-fabric optimization thrust, this thesis describes the concept of “mixed-fabric optimization” and presents several novel optimization techniques for improved design performance, power, area, reliability and turnaround time. First, we propose an optimization flow for implementation of design blocks with mixed non-integer multiple cell heights, achieving an improved tradeoff of performance, power and area. Second, we exploit the dual-Vth libraries and propose a “no-loop” predictive useful skew optimization flow. Last, we integrate dies with different process conditions in a 3DIC, and apply mix-and-match-aware design optimization to improve performance and reliability of 3DICs.