UC San Diego

Current measurement front-ends are widely used to provide a high precision, real-time signal acquisition for biological applications where charge perturbations occur during biological interactions. The requirement of the high dynamic range in front-ends has become imperative for high sensitivity biosensors; however, designing front-ends with high dynamic range is challenging in advanced CMOS process nodes with reduced supply voltages where the minimum and maximum detectable signals are determined by circuit noise and power supply voltage, respectively.

In this dissertation, I present several ultra-low noise current measurement front-ends for biosensing applications that aim to address this issue. The first work was designed for nanopore-based DNA sequencing. A hybrid semi-digital transimpedance amplifier senses the minute current signatures introduced by single-stranded DNA (ss-DNA) translocating through a nanopore, while discharging the baseline current using a semi-digital feedback loop. The amplifier achieves fast settling by adaptively tuning a DC compensation current when a step input is detected. A noise cancellation technique reduces the total input-referred current noise caused by the parasitic input capacitance. The amplifier has 31.6 MΩ mid-band gain, 950 kHz bandwidth, and 8.5 fA/√Hz input-referred current noise, a 2× noise reduction due to the noise cancellation technique. This system is demonstrated by capturing ssDNA translocation events.

The second front-end is a new current-input analog-to-digital converter (ADC) architecture, an asynchronous Hourglass structure that provides both low-noise amplification while decoupling the maximum detectable signal from the supply voltage, and first-order quantization noise-shaping. By eliminating the need for the reset switch in a capacitive transimpedance amplifier (C-TIA) and the feedback digital-to-analog converter in a delta-sigma modulator and compensating the excess loop delay, this Hourglass ADC achieves over 160 dB dynamic range (sub-pA to >10 µA), sub-pArms input-referred noise, and a conversion time of 400 ms – 2.5× faster than the state-of-the-art.

The linearity and power efficiency of the Hourglass ADC is further improved when implementing the ADC in a closed loop structure where a predictive I-DAC provides a coarse estimate of the current and the Hourglass ADC processes only the residue. A calibration technique is proposed to optimize the power consumption in the C-TIA and improve the current-to-frequency (I-to-F) linearity. This closed-loop Hourglass ADC achieved Shreier FOM of 197 dB with a 7 ppm linearity error over a 160 dB dynamic range from 100 fA to 10 µA.