UC San Diego

As the conventional bulk CMOS shrinks towards the deep sub -100 nm regime, the advantages of scaling are seriously limited by a series of adverse effects such as random dopant fluctuation, short-channel effects, and mobility degradation primarily due to the high substrate doping level required in ultra small devices. As a solution to extend the scaling limit further, FinFETs have become an important subject of intensive VLSI research. In this dissertation, the analytic potential model for symmetric double-gate MOSFETs is verified and calibrated with experimental n- and p-channel FinFETs over a wide range of gate lengths. Quantum mechanical effects are incorporated in the model to reproduce the measured Cg-Vgs data of n- and p-channel FinFETs. Finite inversion layer thickness due to quantum mechanical carrier confinement at high gate overdrives becomes non-negligible for very thin oxides. The increase of effective oxide thickness degrades the gate capacitance and the drain current. The long-channel mobility is modeled by including both a phonon scattering term and a Coulomb scattering term with opposite field dependence. They are extracted from the mobility degradations in the low and high field regions respectively. The dependence of normalized drain current on gate length at low drain bias reveals that there is a slight mobility dependence on gate length due to different strain effects in n- and p-channel FinFETs respectively. In order to obtain the intrinsic mobility, Shift-and-Ratio method is applied to separate out the source-drain series resistance effects. A useful coefficient is defined and extracted to quantitatively indicate the change of mobility from its long-channel value. The coefficient indicates that the electron mobility is degraded as the gate length decreases, whereas the hole mobility is enhanced due to relaxation of the tensile strain induced by the metal gate. The short-channel model for symmetric double-gate MOSFETs based on the analytic solution to 2-D Poisson's equation is validated in terms of the measured drain-induced barrier lowering, the threshold voltage roll -off, and the subthreshold current slope of sub-100 nm FinFETs. The difference between the extracted effective channel length and the drawn gate length is nearly the same for n- and p-channel FinFETs. Other high-field effects including the channel length modulation and velocity saturation are also incorporated into the model to reproduce the drain current data at high drain bias