UC Santa Cruz

Distributed inductor-capacitor (LC) resonant clocking is a recent, promising technique to reduce the energy consumption in Clock Distribution Networks (CDNs) by recycling the energy on-chip. Even though the majority of power is saved, resonant clocks distribute a sinusoidal clock signal with a 25% slew which increases short-circuit power in the sequential elements compared to traditional buffered clocks. In this work, we present the first harmonic resonant clock circuit that adds a third harmonic to the fundamental frequency in order to increase the slew rate of resonant clocks and reduce the short-circuit power in the sequential elements. We present two different methods of tuning a secondary tank circuit in a Colpitts oscillator to minimize the slew: one based on the frequency response of the circuit and the other based on matching an ideal square wave clock signal. Both methods provide benefits in slew reduction at a modest cost of components.