Donald Bren School of Information and Computer Sciences

In this document the architecture and instruction set of a RISC-Core is designed in a top down fashion so ANSI-C-programs are easily processed on the core giving optimal performance with a minimum of architectural features. Severe constraints have to be obeyed concerning register size, instruction-coding and addressing, limitation resulting from the goal of a small area of the core and easy memory interfacing. Compiler design and architecture engineering is done concurrently, influencing each other and showing strong interdependence of instruction set, architecture and compiler. The LCC- retargetable compiler is used as a basis and the machine description file is elaborated. A retargetable assembler is taken from an existing design with a new instruction description file. The core is simulated with an existing, retargetable C- based simulator.