UC San Diego

In this paper, various methods were tested to facilitate the creation of copper-based printed circuit boards manufactured on a SiO2 quartz substrate for use in low-temperature and low-background applications as part of the nEXO collaboration. This technology will be employed for front-end circuitry within the nEXO machinery for the purposes of maximizing the experiment’s sensitivity and being able to identify and measure neutrinoless double beta decay. To identify failure modes, samples were fabricated, characterized, then stress tested mechanically and through submersion into liquid nitrogen. Further samples were thermally cycled between room temperature and -100oC. Thermal cycling was conducted across two metallization schemes: 100 nm copper directly on quartz and 100nm copper deposited onto a 10nm chromium interlayer, which itself was deposited onto quartz. As a result, the Cu-SiO2 interface was demonstrated to be physically weak, both in terms of its ability to maintain a bond across thermal cycles and its tendency to be easily scraped and damaged by any significant physical pressure. In contrast, the system with a chromium interlayer exhibited much greater physical resilience, with far fewer cases of damage to the traces themselves. In the absence of physical damage and extreme strain, both sets of samples were observed to have stable resistance values. However, the resistances of all copper traces are substantially higher than the theoretical values of bulk copper, and the chromium interlayer has a nontrivial rate of failure. Thus, more research will be needed to identify the best interlayer for use in this circuitry.