Laboratory for Manufacturing and Sustainability

CMP has been successfully used for shallow trench isolation (STI) process in front end semiconductor processing. In STI process, nitride covers active device area acting as the CMP stop layer. Amount of nitride erosion during CMP is directly related to the step height of oxide isolation structure after removing nitride, and affects device performance as well. As semiconductor technology node is decreasing beyond 90nm, variation of nitride erosion over a chip in CMP process should be controlled within tight specifications. A model based simulation tool for chip scale variation of nitride erosion would improve not only CMP compatible STI layout design but also help in optimization of high density plasma chemical vapor deposition (HDPCVD) process of oxide layer. In this paper, a chip scale modeling scheme for better prediction of nitride erosion map integrating HDPCVD oxide topography is presented. In addition, a simulation result for a specially designed test pattern resembling production level STI layout is presented.