UC Davis

As the performance gains from Moore’s Law are slowing down, the demand for computational power, driven primarily by artificial intelligence (AI) and machine learning, continues to rise exponentially. Modern AI models, which require orders of magnitude more floating-point operations than their predecessors, face a growing mismatch between computational demand and improvements in traditional silicon-based microelectronics. In parallel, data centers and high-performance computing (HPC) systems are experiencing surging data traffic, expected to grow by 80% annually, and are projected to consume as much as 13% of global electricity by 2030. These trends highlight the urgent need for more energy-efficient, scalable, and low-latency data communication solutions within data centers and computing infrastructures. Silicon photonics (SiPh) and co-packaged optics are transformative technologies that can potentially address the aforementioned challenges inherent in traditional electronic architectures.

This dissertation firstly presents the demonstration of monolithic silicon photonic Thin-CLOS LIONS, an arrayed waveguide grating router (AWGR) based optical fabric that enables scalable, low-latency, high-bandwidth, strictly non-blocking all-to-all communications among computing nodes. A novel multi-layer waveguide routing technique is developed to compactly integrate the AWGRs and connection waveguides on a single chip. Light is coupled between layers through high-efficiency tri-layer vertical couplers while minimizing cross-layer insertion loss and crosstalk. The fabricated 32×32 SiPh Thin-CLOS LIONS prototype demonstrates error-free (BER< 10−12) optical data routing operation at 25 Gb/s, with minimal power penalty.

Secondly, a heterogeneously Direct Bond Interconnect (DBI) 3D electronic-photonic integrated circuit (EPIC) transceiver enabling 32-WDM is demonstrated to provide energy-efficient and high-bandwidth optical datalinks capable of interfacing the Thin-CLOS core layer. The PIC and EIC are co-designed and fabricated using AIM Photonics Active photonics technology and GlobalFoundries 12LP process, respectively. With SerDes, TIA, and drivers integrated on-package, the transceiver achieves a record-high energy efficiency of 496 fJ/bit at 18 Gb/s, showcasing the great potential of electronic-photonic integration for computing power scaling.

Third, a co-designed silicon photonic polarization stabilizer circuit is demonstrated to ensure the optical interconnects discussed above receive TE-polarized signals. The tracking loop is the first monolithically integrated electronic photonic polarization stabilizer demonstrated, with photonic circuits, ADC, feedback control circuitry, and DACs integrated on the same chip. The circuit is fabricated using the GlobalFoundries 90WG CMOS-Photonic process, stabilizing polarization scrambled up to 1256 rad/s while ensuring error-free data transmission at 10 Gb/s.

Lastly, a nano Ge-on-Si weakly resonant Fabry-Perot photodetector that operates at 38 Gbps with low dark current (0.72 nA under -1V bias) and high responsivity (0.93 A/W at -1V bias) is demonstrated as a solution for ultra-high sensitivity light detection in photonic transceivers.