The analysis and design of two novel high-speed CMOS clock dividers is discussed. The realizations of these circuits in a 0.13-mu m CMOS process show a significant improvement in high-frequency operation compared to a conventional D flip-flop-based divider. Measured sensitivity curves of these dividers give maximum frequency of operation ranging from 20 to 38 GHz with power consumption of 12 mW from a 1.8-V supply voltage.

A 34 Gb/s 2:1 serializer consisting of a CMOS MUX and CMU using a 0.18 mu m SiGe BiCMOS process is presented. The serializer is based on distributed amplifier topology realized using spiral inductors. The circuit also includes an on-chip 2-channel 2(7) - 1 PRBS generator. The 34 Gb/s serial output has single-ended voltage swing of 380 mV with rise/fall time of 13 ps, and measured ISI is less than 5 ps p-p.