UC San Diego

Frequency conversion circuits are prevalent in modern system-on-chips. In RF receivers, for example, mixers are used to downconvert transmitted data from RF to IF or baseband. In phase-locked loops (PLLs) that generate clocks for these mixers, dividers are used to downconvert PLL output clocks to match the frequency of the reference clock. In all of these applications, aliasing caused by harmonics of the clock can degrade system performance, leading to reduced SNDR in receivers and increased close-in phase noise in PLLs.This dissertation presents three methods to alleviate the issues caused by clock harmonics. First, a linearized $Q$-boosted LNA is used to provide sharp bandpass filtering before the mixer, attenuating unwanted noise and blockers prior to aliasing. Second, an all-passive harmonic combination structure is proposed in a mixer-first receiver to attenuate the clock harmonics themselves, thereby reducing aliased blockers. Finally, a digital implementation of injection locking is used in PLL to provide useful information to divider subsampling harmonics, recycling the harmonic conversion gain to the gain in baseband that helps to increase loop bandwidth. Additionally, a computationally efficient algorithm is developed to accurately compute the output noise of a linear periodically time-varying discrete-time system, considering the cross-correlated frequency-shifted spectrum of cyclostationary noise. These proposed methods significantly mitigate the issue of system performance degradation due to aliasing in frequency conversion circuits.