UC Davis

Millimeter-Wave (mmWave) Integrated Circuit (IC) design has become a promising research topic since last decade. Millimeter-Wave signals (30GHz to 300GHz) benefit from ultra-high bandwidth and unique physical attributes. With the portability brought by IC techniques, mm-wave chips have enabled applications such as ultra-high-speed (5G/6G) communications, mobile satellite communications, Internet-of-Things (IoT) sensors, ultra-high-resolution radar and various kinds of dieletric, biomedical and chemical sensors. However, with stringent power budget of portable devices and the power-hungry attribute of mmWave circuits, low-power and low-noise on-chip mmWave signal generation and radar design are faced with great challenges.In the first part of this dissertation, a new mmWave frequency synthesizer structure is proposed. Based on Sub-Sampling Phase-Locked Loop (SSPLL) technique, the generated signal achieves low in-band phase-noise. With the proposed dividerless frequency acquisition technique based on a Sub-Sampling Lock Detector (SSLD) and on-chip intermediate-frequency PLL (IF-PLL), the SSPLL can automatically detect its lock status and lock to the correct target frequency without using power-hungry mmWave Injection-Locking Frequency Dividers (ILFD). To verify the proposed system, a prototype 40.5GHz SSPLL chip has been taped out in 65nm CMOS. Due to the relatively low-frequency operation and moderate noise requirement of IF-PLL, as well as the low-power SSLD, the proposed system achieves low power consumption and jitter simultaneously. The measured results show an 8.8mW power consumption and 228fs RMS jitter with in-band and out-band phase noise of -96.6dBc/Hz at 1MHz offset and -106.9dBc/Hz at 10MHz offset, respectively. Another critical issue of charge pump (CP) current mismatch and its exclusive effects on SSPLL are presented in this dissertation. Transistor’s channel-length-modulation (CLM) effect induces SSPLL loop gain distortion and decreases VCO control voltage (Vctrl) locking range (LR). A feedback based compensation method, which is the first-published solution to SSPLL CP mismatch, is then proposed. In a prototype mmWave SSPLL with the proposed compensated CP, the CLM effect is cancelled and Vctrl LR is extended from 0.50V to 0.75V under a 1V supply, without degrading SSPLL noise performance much. As a result of the more efficient use of Vctrl range, VCO capacitor bank setup number is reduced from 10 to 7 to cover the same 10% total tuning range. The compensation circuitry consumes only 0.36mW power. The prototype 40.5GHz SSPLL consumes only 9.5mW power with 192fs RMS jitter. Radar sensors with ultra-high range resolutions have great potential in non-contact sensing of human vital signs, biomedical signals, material thickness and mechanical vibration, and in imaging. With short wavelengths for high resolution and relatively simple structure, mmWave Doppler radar has become a competitive candidate in various displacement-sensing applications. However, issues like detection nulls, nonlinear gain and quadrature signal paths mismatch limit the performance of mmWave Doppler radar. In the last part of this dissertation, a novel system structure of Doppler radar front end is proposed utilizing the intrinsic low added in-band noise feature of SSPLL and a proposed quadrature-less demodulation method. A prototype 110mW 39GHz Doppler radar front end in 65nm CMOS for displacement and vibration sensing is presented. Sub-sampling PLLs (SSPLL) generate single-tone radiated signal. A proposed phase demodulator (PDM) uses coherent IF demodulation to convert displacement to a DC/baseband signal with constant gain. Detection nulls in conventional Doppler radars are eliminated without using quadrature demodulation. The prototype radar achieves 4µm static and 77nm vibrational (at 10KHz) range resolutions.