The ever-increasing demand for ultra-high-speed interconnects has driven the development of wireline transceivers operating at >100Gbps per lane. As a major contribution of data random jitter, clock-dependant distortion of transmitters and receivers, the clock generation and distribution circuits in SerDes becomes increasingly complex and time-consuming with stringent specifications, especially considering the fast development of technology nodes of the FinFET processes. This thesis focuses on the design of energy-efficient clock generation and distribution network with generator-based design methodology using Berkeley Analog Generator, which speeds up the design procedure, while satisfying the performance requirements.

A bang-bang phase-locked loop generator for 28/32Gbps SerDes that encapsulates this design methodologies for its circuit blocks and the complete PLL system is first reported. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

Furthermore, a flexible clock distribution network for a 200Gbps pulse amplitude modulation four-level transmitter is designed using the layout generators in 28nm CMOS technology. The proposed TX achieves an eye opening with >52.9mV eye height, 0.36UI eye width, >98% RLM and 4.63pJ/b at 200Gbps PAM-4 signaling under >6dB channel loss at 50GHz, demonstrating the highest data rate achieved using a planar process.

To complete the whole TX design, a layout generator for sub-100fs sub-sampling PLL is proposed. With a type-I loop and tri-state integral path, the voltage ripples of the hybrid loop is eliminated and the PLL reaches a RMS jitter of 44fs at 28GHz output, a spur of -56.6dB, which results in the FOM value -254.8dB. Finally, the PLL is merged with the transmitter data path, achieving 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under ~6dB channel loss at 50GHz, showing the capability of the generator-based design methodology.