Several benchmarks for measuring memory performance of HPC systems along dimensions of spatial and temporal memory locality have recently been proposed. However, little is understood about the relationships of these benchmarks to real applications and to each other. In this paper, we propose a methodology for producing architecture-neutral characterizations of the spatial and temporal locality exhibited by the memory access patterns of applications. We demonstrate that the results track intuitive notions of spatial and temporal locality on several synthetic and application benchmarks. We employ the methodology to analyze the memory performance components of the HPC Challenge Benchmarks, the Apex-MAP benchmark, and their relationships to each other and other benchmarks and applications. We show that this analysis can be used to both increase understanding of the benchmarks and enhance their usefulness by mapping them, along with applications, to a 2-D space along axes of spatial and temporal locality.

Like all computing platforms, grids are in need of a suite of benchmarks by which they can be evaluated and characterized. As a first step towards this goal, we have developed a set of probes that exercise basic grid operations by simulating simple grid applications. We run these probes on a testbed, collecting performance data such as compute times, network transfer times, and Globus middleware overhead. The results of our experiments help provide insight into the stability, robustness, and performance of this grid testbed, as well as some recommendations for future grid development.

Pre-2018 CSE ID: CS2003-0760