High-speed, high-resolution pipelined ADCs require each pipelined stage's reference circuit to have very low output impedance for accurate reference voltages, often within a small fraction of the amplification phase. However, this results in significant power dissipation in the reference circuit. This thesis presents two digital background calibration techniques that calibrate for reference errors due to incomplete reference setting, reducing power dissipation. Additionally, the reference calibration technique extends to calibrate for second- and third-order reference errors, further reducing required power.

The conventional op amp is replaced with the energy-efficient and high output swing ring amplifier, but published ring amplifiers require external biases to adjust the dead-zone manually, limiting commercial applications. This thesis proposes a method to automatically adjust the dead-zone voltage, overcoming this limitation.