Pre-2018 CSE ID: CS2003-0752

Binary codes and Boolean logic form the foundation of digital computing as we know it. However, the ever-increasing demand for cheap computing power for emerging applications and the advent of novel devices with unique characteristics bring about questions of potential alternatives. This dissertation challenges the status quo by reimagining the established digital/analog boundary and demonstrating how computing with temporal operators can be practical and remarkably efficient.

To this end, the focus is initially on conventional devices. The exploration begins with the idea that digital temporal codes, in which a number is represented by the time that a low to high voltage transition occurs, may, in some cases, be a happy medium between analog and digital binary. To showcase the benefits of this approach, a temporal accelerator for decision trees is developed. The resulting system is built solely with off-the-shelf CMOS components, allows tight integration with sensors, and delivers multiple orders of magnitude energy and performance gains over state-of-the-art solutions.

In the second part of the dissertation, the focus is on post-Moore technologies---specifically, superconductor electronics. Despite their promise as candidates for integrated classical-quantum computers and supercomputers, a fundamental mismatch between traditional computational abstractions and the pulse-based nature of superconductor devices impedes their advancement. Unfortunately, transient voltage pulses do not translate to 0s and 1s as easy as stable voltage levels. Fortunately, temporal operators do not use binary inputs. The advantages of avoiding pulse-to-binary translations at the gate level are highlighted through a series of temporal superconductor designs. Interestingly, these advantages carry over to Boolean superconductor designs by leveraging a newfound duality between temporal and Boolean operators.

The dissertation concludes with a discussion of superconducting information storage in the time domain and the generalization of temporal formalism in a way that allows the specification of both hardware and its properties using the same temporal operators.

Pre-2018 CSE ID: CS2000-0656

Pre-2018 CSE ID: CS2001-0678

Pre-2018 CSE ID: CS2000-0649

For highly critical workloads, the legitimate fear of catastrophic failure leads to both highly

conservative design practices and excessive assurance costs. One import part of the problem is

that modern machines, while providing impressive performance and efficiency, are difficult to

reason about formally. We explore the microarchitectural support needed to create a machine

with a compact and well defined semantics, lowering the difficulty of sound and compositional

reasoning across the hardware/software interface. Specifically, we explore implementation

options for a machine organization devoid of programmer-visible memory, registers, or state

update, built instead around function primitives. The resulting machine can be precisely and

mathematically described in a brief set of semantics, which we quantitatively and qualitatively

demonstrate is amenable to software proofs at the binary level.

As time continues, we become increasingly dependent on computational devices for all

facets of our lives — including our health, well-being, and safety. Many of these devices live

“in the wild,” in resource-constrained and/or embedded environments, without access to large

software stacks and heavy language run-times. At the same, increasing trends in heterogeneity

in computer architecture gives the opportunity for new cores in system-on-chips (SoC’s) that

provide support for increasing critical workloads. We propose an implementation and provide

an evaluation of such a device, the Zarf Architecture for Recursive Functions (Zarf), provid-

ing a interface of reduced semantic complexity at the ISA level, giving designers a platform

amenable to reasoning and static analysis. The described prototype is comparable to normal

embedded systems in size and resource usage, but it is far easier to reason about programs

according to analysis. This can serve both resource-constrained devices, providing a new hard-

ware platform, and resource-rich SoC’s, serving as a small, trusted co-processor that can handle

critical workloads in the larger ecosystem.

Different layers of the computer system, from the low-level hardware accelerators and networks-on-chip (NoC) in multi-core systems, to the upper-level operating systems and software applications, rely on the sharing of hardware computing resources. Unfortunately such sharing, when not carefully managed, can introduce a host of protection problems and sources of information leakage. We describe a set of methods by which it is possible to systematically scale performance via hardware sharing without exacerbating security properties by being aware of the design and characteristics of individual layers and components. The key to this is efficiently dealing with security vulnerabilities introduced by sharing in terms of time and space through the creation of new security-conscious sharing interfaces. In a systematic way is to first define coordination techniques into more detailed patterns, and by bridging the gap of less efficient universal measures with provably more performant and secure patterns.

Specifically we demonstrate the usefulness of a sharing pattern for hardware and software systems where separation is of concern (interference and timing channel mitigation, etc). The most important insight is that in order to fully utilize computing resources (to improve performance and availability), the entities that share these resources must coordinate in a pre-calculated way. More dynamic approaches to improve performance and concurrency are likely to introduce new interference in the system. While we show that certain static scheduling measures in lower level hardware such as networks-on-chip can provably eliminate timing channels, the dynamic nature of software systems makes covert channels harder to be confined. Besides, software systems also face other types of security problems beyond side channels. To improve concurrency and performance without exacerbating security requires a slightly different approach.

To study the obstacles that hinder software applications' scaling in a system because of security concerns, we delve into the Android operating system and its appification ecosystem structure. A prime avenue for attack is introduced because of its distributed sharing eco-pattern. We propose a centralized approach with a single reliable service as a method to enable computation reuse among applications. The proposed centralization technique favors well-protected application-to-system communications over vulnerable application-to-application communications. Thus not only computation concurrency is boosted but also the possibility of an app being attacked through the attack-prone Inter-Component Calls (ICCs) due to possible distributed computation sharing is eliminated. This approach further enables improvements to security with the addition of a novel application-centric grouping for isolation. We show through a prototype on Android how our approach supports and protects inter-app resource sharing, while improving concurrency at scale.

Simultaneous Localization and Mapping (SLAM) describes a class of problems facing a large and growing field of autonomous systems -- from self-driving cars, to interplanetary rovers, to home automation products. Unfortunately this is a complex task where sophisticated algorithms and data structures are required to navigate a wide range of uncharted environments. Furthermore, most mobile robots need to run these tasks near real-time onboard an embedded controller with limited power and compute resources. To address this problem we explore the stochastic gradient descent (SGD) variant of graph solvers for SLAM and observe a tradeoff between various execution architectures and overall execution speed. Based on these observations, we propose a custom multiprocessor design that relaxes memory-coherency constraints between parallel cores while avoiding divergent behavior. We introduce a specialized streaming-tree interconnect that provides increased performance while using fewer resources compared to state-of-art GPU/CPU implementations of SGD. Finally, we discuss applications of unconventional architectural paradigms like over-provisioned “dark processors” and specialized data partitioning that provided a unique performance advantage for our particular design.

Computation is increasingly complex, and our languages, systems, and design practices are changing to meet that shifting reality. That shift comes also with new challenges in debugging and optimization. In this thesis, we demonstrate that by adopting performance-driven analysis and optimization around communication paradigms, we are able to facilitate the development process and improve the performance of the programs. Specifically, we show such improvements in improving the synchronization mechanism in Golang by Hardware Transactional Memory (HTM), analyzing the complex system within datacenter by Critical Path Analysis (CPA) of Remote Procedure Call (RPC), and optimizing programs by novel service of prediction at Operating System (OS) level.

As computing continues to be used for increasingly private and sensitive operations impacting all aspects of our lives, the need to maintain tight control of those computations only continues to grow. This, when coupled with the increasing trend of “outsourced’' computation where datacenters are responsible for both storing data and performing computations over it on behalf of another party, naturally raises the level of importance of security and privacy even further. As such, algorithmic approaches to privacy-preserving and secure/trusted computations are rapidly emerging as a key aspect of workloads in datacenters at all scales. The higher cost associated with this additional algorithmic complexity will only increase the power consumption of these data centers, which are already receiving significant scrutiny for their ever more power-intensive operation. Architectural solutions are needed to support these emerging aspect of workloads. With the decline of Moore’s Law, this also presents an interesting prospect for several energy-efficient “Post-Moore” technologies such superconducting electronics and steep-slope devices which are studied and developed as potential replacements for Silicon-based CMOS to realize low power datacenter processors and accelerators.

In this dissertation, we study new opportunities for architectural support of these emerging application needs in both traditional and emerging technologies. To perform this work we need to make additional contributions advancing the modeling and evaluation of emerging Post-Moore technologies in the context of secure privacy-preserving computations. First, we show how using a small, co-located, trusted hardware device can be used to improve multiparty computation-based operations based on the trade-off of physical security and performance. Second, we show how near-data processing can be exploited to improve certain forms of homomorphic encryption with applications in private search. Finally, we explore how these emerging technologies can be used to improve energy-efficiency of datacenter workloads by modeling accelerators and multicore processors.