The transistor density continues to increase exponentially, but the power dissipation per transistor improves only slightly with each generation of Moore’s law. Given the constant chip-level power budgets, this exponentially decreases the fraction of the transistors that can be active simultaneously with each technology generation. Hence, while the area budget continues to increase exponentially, the power budget has become a first-order design constraint in current processors. In this regime, utilizing transistors to design specialized cores that optimize energy-per-computation becomes an effective approach to improve the system performance. To trade transistors for energy efficiency in a scalable manner, we propose quasi application-specific integrated circuits, or QASICs, specialized processors capable of executing multiple general- purpose applications while providing an order-of-magnitude more energy efficiency than a general-purpose processor. The QASIC design flow is based on the insight that similar code-patterns exist across applications. Our approach seeks to exploit these similar code patterns to design specialized cores that can support many of the widely used computations. Our results demonstrate that designing relatively few QASICs can support operator functions of multiple commonly used data structures and these QASICs provide 13.5× energy savings over a general-purpose processor. On a more diverse workload consist- ing of twelve applications selected from different application do- mains (including SPECINT, Sat Solver, Vision, EEMBC, among others), our results show that QASICs reduce the required number of application-specific circuits by over 50% and the area requirement by 23% compared to the fully-specialized logic while providing energy-efficiency within 1.27X of that of fully-specialized logic. Also, at system level, our approach reduces the application energy-delay metric by 46% compared to conventional processors.

Pre-2018 CSE ID: CS2011-0964

Power over-subscription can reduce costs for modern data centers. However, designing the power infrastructure for a lower operating power point than the aggregated peak power of all servers requires dynamic techniques to avoid high peak power costs and, even worse, tripping circuit breakers. This work presents an architecture for distributed per-server UPSs that stores energy during low activity periods and uses this energy during power spikes. This work advocates explicit sizing of the distributed UPS batteries for power capping and provides a methodology to properly select the properties of the battery in order to reduce total datacenter cost of ownership per server. Depending on workload diurnal patterns and oversubscription assumption this approach can achieve up 5-10% reduction in overall costs per server.

Pre-2018 CSE ID: CS2012-0985

Transactions have emerged as a promising way to exploit thread-level parallelism in the presence of shared data. Preventing data-races between threads traditionally implies lock-based synchronization. This comes at the risk of deadlock due to programmer error, and overly-conservative locking will limit the performance potential of parallel execution. Transactions circumvent these limitations by detecting and serializing data dependencies between threads at runtime without the need for locks. Hardware supported transactional memory builds on top of the cache coherence mechanism of shared memory multi-processors to detect data dependence conflicts between concurrent transactions. Recent proposals address the need to support the virtualization of transactions when the finite capacity of the cache is exceeded. These techniques have either a fast commit or abort, but not both. Similarly they support either fast conflict detection but are not able to handle swapped processes, or slow but complete. In this paper we examine page-based transactional memory to provide virtual transactions. We combine transaction bookkeeping with page address translation for fast conflict detection with fast access of overflowed transactional data. Our approach provides fast virtual transaction commit and abort, and conflict detection. We provide quantitative measurement of performance, whereas most examinations of virtualized transaction techniques provide only theoretical analysis of performance.

Pre-2018 CSE ID: CS2005-0848