This work demonstrates the design of a MMIC solid state class-A power amplifier in 250nm InP HBT technology achieving 0.5W saturated output power at 238 GHz at compressed gain of 14dB and power added efficiency of 10%. The 3dB bandwidth is 230 GHz to 242GHz. The power amplifier uses 4:1 travelling wave combiner to combine the output power of 8 power cells. Each power cell is a 3-stage cascaded amplifier with 2 common-base gain stage and 1 common emitter power stage.

Demand for wireless data transfer has been increasing rapidly with the rise of smart devices and mobile video streaming. With dozens of wireless applications currently in use and only a finite bandwidth to work with, engineers are challenged to both expand the upward frequency limit of high-performance, high-efficiency wireless systems and to increase the spectral efficiency of the frequency bands already in use. The development of deep sub-um silicon-on-insulator transistor technology and powerful computer-aided circuit designing tools have allowed us to create more affordable silicon-based phased array ICs at frequencies previously achievable by only military applications. The 5th generation of mobile systems (5G) is now expected to use this type of IC to offer increased wireless data capacity in densely-populated areas using mm-wave frequencies. Demand for wireless data is only expected to continue rising, particularly as new IoT applications such as autonomous vehicles become commercially viable.

The work presented in this dissertation addresses both the need for expanding the usable frequency spectrum and the need to increase spectral efficiency in available bands. It includes a design for an analog beamforming matrix for a spatially multiplexed phased array receiver in silicon SOI technology, low-power high-linearity w-band amplifiers in InP HBT technology, and ultra-wideband mm-wave power amplifiers in InP HBT technology. Spatially multiplexed phased array transceivers have the potential to greatly increase the spectral efficiency of mm-wave frequency bands by re-using frequency spectrum for many data channels. This type of system can be used to create short-range high-capacity line-of-sight wireless backhaul for crowded city squares or event venues. Mm-wave power amplifiers and high-linearity amplifiers in new 130 nm InP HBT technology represent an IC performance boost which pushes the frequency limits of feasible power-efficient wireless systems.

The measured power amplifier ICs produce output power of larger than 16.5 dBm at the 3-dB gain compression condition from 50 GHz to 100 GHz, and a small signal gain of 15 dB over a 90 GHz 3-dB bandwidth. The peak power-added efficiency (PAE) is larger than 8% over that same frequency range. At 90 GHz, the ICs produce 22 dBm of saturated output power and 14.7% PAE. The measured high-linearity amplifier ICs demonstrate an output-referred 3rd order intercept (OIP3) of 22 dBm, a gain of 6.4 dB, and a noise figure below 7 dB at 100 GHz. New designs for an analog MIMO beamforming matrix IC, a 100-165 GHz power amplifier, and an improved w-band high-linearity amplifier are also outlined in this dissertation.

In this research, we consider the next-generation systems (100-340GHz), as millimeter frequencies permit a much larger spectrum, and shorter wavelengths provide massive MIMO array and high image resolution. This thesis focuses on building the hardware and necessary components for such systems. It is very challenging to produce decent efficiency and power at mm-wave frequencies as the gain drops significantly and the loss increases. Additionally, mm-wave packaging requires advanced assembly techniques. Here, we introduce a network theory to analyze the amplifier design options for the maximum PAE. The proposed theory considers the stacking and parallel power approaches using two-port techniques. This theory establishes a design framework for designing high-efficiency power amplifiers. We demonstrate record efficiency mm-wave power amplifiers (140, 210, and 300GHz) with moderate output power. The 140GHz amplifiers produce measured output power (20.5-23dBm) with a record efficiency of 17.8-20.8% PAE. We present 17.7-18.5dBm output power over the 190-210GHz frequency range with high efficiency of 6.9-8.5% PAE. Finally, a massive MIMO demonstration and mm-wave packaging are presented. We started with on-waver CMOS transmitters and receivers, then moved to a single packaged CMOS channel transmitter with eight-element series fed patch antenna, which has an EIRP of 13dBm at 135GHz. Finally, we built, in fabrication, a tile holding eight elements transmitter or receiver. The thesis covered the design and implementation of high-efficient packaged transmitters that prove the feasibility of the mm-wave communication system.

There is an increasing demand for high data-rate wireless communications in endpoint and backhaul links. In this research, we develop next-generation wireless communication systems (200–300 GHz), as millimeter frequencies provide vast amounts of available bandwidth, and shorter wavelengths permit many elements in physically compact arrays. This thesis focuses on building the necessary hardware and infrastructure for such systems.

First, we investigate two important building blocks: low noise amplifiers (LNAs) and frequency multipliers. We present a comprehensive study on multi-stage LNA design based on low total (cascaded) noise figure, i.e., noise measure (NM). 200 GHz LNAs in common-base (CB) and common-emitter (CE) topologies were presented with record noise figure among HBT technologies: 7.4±0.7 dB over 196–216 GHz (CB) and 7.2±0.4 dB over 196–216 GHz (CE). 280 GHz frequency multipliers (8:1 and 16:1) are presented with record spectral purity. The 8:1 frequency multiplier generates −0.6dBm output power and has a 3-dB bandwidth of 48 GHz. Spurious harmonics are suppressed by more than 28 dBc over the 3-dB bandwidth. The 16:1 frequency multiplier generates −0.6dBm output power and has a 3-dB bandwidth of 44 GHz. Spurious harmonics are suppressed by more than 26 dBc over the 3-dB bandwidth.

Next, 200 and 280 GHz broadband transceivers in Teledyne 250nm InP HBT technology are presented. The 280 GHz transmitter IC has a peak conversion gain of 21.6 dB with 36 GHz of 6-dB modulation bandwidth, and dissipates 1535mW. The measured saturated output power is 14.1dBm at 272 GHz. The 280 GHz receiver IC has a peak conversion gain of 22 dB with 34.5 GHz of 6-dB modulation bandwidth, and dissipates 455mW. The measured double sideband (DSB) noise figure is 10.8 dB at 281.5 GHz. These are the record output power and noise figure reported at and around 280 GHz. The 200 GHz transmitter IC has a record output power (15.3–16.5 dBm) and efficiency (2.71–3.57%) over 195–200 GHz. The 200 GHz receiver IC has a record DSB noise figure (7.7–9.3 dB) over 200–212 GHz.

Finally, we demonstrate packaged 200 GHz 1-channel transmitter and receiver modules with series-fed microstrip patch antennas on glass. The packaged transmitter module has effective isotropic radiated power (EIRP) of 21.6dBm with 20 GHz 3-dB modulation bandwidth and 62-degree E-plane and H-plane 3-dB beamwidth. The packaged receiver module has a 14 GHz 3-dB modulation bandwidth and 62-degree E-plane and H-plane 3-dB beamwidth. Modules can support a wide range of modulation schemes (i.e., QPSK, 16QAM). The link measurements at 7.15 meters showed 13.4% error vector magnitude (EVM) during 32Gb/s, 16 quadratic-amplitude modulation (QAM) transmission. The integrated transmitter and receiver modules can be used for a broad range of applications, including wireless backhaul, imaging, and radar applications.

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal-

oxide-semiconductor field-effect transistors (MOSFETs) are promising candidates

for replacing Si-based MOSFETs for future very-large-scale integration (VLSI)

logic applications. III-V InGaAs materials have low electron effective mass and

high electron velocity, allowing higher on-state current at lower VDD and reducing

the switching power consumption. However, III-V InGaAs materials have a nar-

rower band gap and higher permittivity, leading to large band-to-band tunneling

(BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the

channel, and large subthreshold leakage due to worse electrostatic integrity. To

utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high

on-state performance over Si MOSFETs as well as very low leakage current and

low standby power consumption. In this dissertation, we will report InGaAs/InAs

ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in

InGaAs/InAs MOSFETs are reported as described below.

1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match

to InP by molecular beam epitaxy (MBE), and studied the electron transport

in In0.53Ga0.47As/AlAs0.44Sb0.56 heterostructures. The InGaAs channel MOS-

FETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52Al0.48As barriers

were demonstrated, showing significant suppression on the back barrier leakage.

2) Ultra-thin channels: We investigated the electron transport in InGaAs and

InAs ultra-thin quantum wells and ultra-thin body MOSFETs (tch∼2-4 nm).

For high performance logic, InAs channels enable higher on-state current, while

for low power logic, InGaAs channels allow lower BTBT leakage current.

3) Source/Drain engineering: We developed raised InGaAs and recessed InP

source/drain spacers. The raised InGaAs source/drain spacers improve electro-

statics, reducing subthreshold leakage, and smooth the electric field near drain,

reducing BTBT leakage. With further replacement of raised InGaAs spacers by

recessed, doping-graded InP spacers at high field regions, BTBT leakage can be

reduced ∼100:1.

Using the above-mentioned techniques, record high performance InAs MOS-

FETs with a 2.7 nm InAs channel and a ZrO2 gate dielectric were demonstrated

with Ion = 500 µA/µm at Ioff = 100 nA/µm and VDS =0.5 V, showing the highest

on-state performance among all the III-V MOSFETs and comparable performance

to 22 nm Si FinFETs. Record low leakage InGaAs MOSFETs with recessed InP

source/drain spacers were also demonstrated with minimum Ioff = 60 pA/µm at

30 nm-Lg , and Ion = 150 µA/µm at Ioff = 1 nA/µm and VDS =0.5 V. This re-

cessed InP source/drain spacer technique improves device scalability and enables

III-V MOSFETs for low standby power logic applications. Furthermore, ultra-

thin InAs channel MOSFETs were fabricated on Si substrates, exhibiting high

yield and high transconductance gm ∼2.0 mS/µm at 20 nm-Lg and VDS =0.5 V.

With further scaling of gate lengths, a 12 nm-Lg III-V MOSFET has shown max-

imum Ion/Ioff ratio ∼8.3×10 5 , confirming that III-V MOSFETs are scalable to

sub-10-nm technology nodes.

This work presents the efforts pursued to optimize InP HBTs for power amplifiers above 100 GHz. Emitter width We reduction to sub-100nm dimension is achieved using a novel cosputtered Ti4wt%W emitter metal, and high power ICP dry etching. The cosputtering process enables fine-tuning of TiW alloy composition for vertical dry etch profile along sidewalls of the 600nm tall emitter metal, retaining sub-100nm emitter width from top to bottom. Base contacts are formed by low-temperature MOCVD regrowth (490 ◦C) of thick p-GaAs (> 4 × 20 cm−3) extrinsic base on the intrinsic p-InGaAs or pGaAsSb base layer, and subsequent UV i-line lift-off of e-beam deposited Pt/Ti/Pd/Au metal stack. Low overall base contact resistivity ρb,c is extracted by TLM on scaled sub100nm We DC “large area” devices to be 0.98 ± 0.4Ω-um2, which meets the requirement for >2THz fmax scaling. The larger bandgap of p-GaAs allows direct abutment of the regrown extrinsic base against sides of the n-InP emitter semiconductor, while blocking undesired electron injection into the extrinsic base. The extended regrown extrinsic base, thus, lowers Rgap by a factor of >2 between the base contact metal and emitter semiconductor, a significant contributor to Rbb in deep submicron HBTs, thanks to themuch lower sheet resistance of the extrinsic base (ρs,ex < 300Ω/sq). Hydrogen passivation of carbon dopants in the p-InGaAs intrinsic base layer is found, and partially reversed with an in-situ N2 anneal in MOCVD before temperature ramp down. Lateral hydrogen out-diffusion is believed to limit carbon dopant reactivation as the smallest We devices showed the lowest apparent intrinsic base sheet resistance (ρs,in = 1900Ω/sq) after the N2 anneal. While the added base spreading resistance Rspread underneath emitter semiconductor is manageable in sub-100nm We devices, DC devices with a GaAsSb intrinsic base are studied as a passivation-proof alternative to InGaAs for maximum Rbb scaling. Collector-base capacitance Ccb scaling is intentionally excluded in this work, so is vertical epitaxial scaling for higher fT , as both face challenges in terms of lithographic and semiconductor doping limits. RF device integration faced tremendous logistic difficulties due to the pandemic lockdown. Nevertheless, working RF devices with fmax in excess of 300GHz are demonstrated. In addition, a detailed review of conventional InP HBT scaling roadmap shows drawbacks of continued Ccb, and fT scaling in sub-100nm We process (e.g., high Rgap, and stagnating Ccb) previously overlooked due to simplified assumptions. It can be shown that conventional beyond-130-nm technology nodes offer comparable or worse device performance, a trend that can be reversed by the insertion of the regrown extrinsic base process module already a reality in SiGe HBT.

Power/heat density becomes excessive in VLSI. Supply voltage in the current 7/10 nm process has been scaled to 0.7 V for logic devices to reduce dynamic power loss (Pdynamic ∝ CwireVdd^2). The low supply voltage (Vdd), on the other hand, poses a challenge to static power loss (Pstatic = IoffVdd), because off-current (Ioff) is limited by the Boltzmann tail of the Fermi-Dirac distribution, corresponding to a minimum 60 mV/dec subthreshold swing SS at room temperature. To scale Vdd to 0.3 V while maintaining a 6 decades on/off ratio, transistors need to have a subthreshold slope (SS) < 60 mV/dec. The tunneling field effect transistor (TFET) is one technology that holds such promise as electron tunneling is not constrained by thermal statistics. Current state-of-the-art TFETs, however, have low on current (Ion) ≈ 10 µA/µm at Vdd = 0.3 V that precludes their applications in actual circuits. In this work, an InP-based triple heterojunction (3-HJ) TFET design is proposed to significantly increase Ion by exploiting a minimized tunneling distance, as well as resonant states in the 3-HJ. PNPN doping profile is employed in 3-HJ TFETs to eliminate the need for an ultra-thin body to ease processing. The simulated Ion reaches ≈ 300 µA/µm at Vdd = 0.3 V. To realize 3-HJ TFETs, three generations of device structures are tried. The main challenges come from the incompatibility between process modules within a small/limited process window. Among all device structures, the qualitative high-k/channel interface and gate metallization is important for high TFET performances. ALD post-metal H2 annealing is developed, and different gate metallization processes, including physical vapor deposition (PVD) of W, Ni, Al, Ti, and atomic layer deposition (ALD) of Ru, TiN, and TiN/Ru, are investigated. With the high-quality ALD TiN/Ru gate as well as the high-k/InP interface, a record low averaged SS of 68 mV/dec for long gate length devices, and a high peak transconductance of 0.75 mS/µm at VDS = 0.6 V in an 80 nm gate length InP channel planar MOSFET are demonstrated. Vertical InP channel MOSFETs and 3-HJ InGaAs/GaAsSb/InAs/InP TFETs with conformal TiN/Ru gate are fabricated using 3rd generation top-down planarization process. A high peak transconductance of 0.42 mS/µm in a 50 nm gate length vertical MOSFET at VDS = 0.6 V, which is comparable with planar MOSFETs at the same gate length, proves the process. The first demonstrated 3-HJ TFETs (having a gate length of 30 nm) show a strong short channel effect, and exhibiting SS of >80 mV/dec at VDS = 0.1 V, and Ion of ≈ 2 µA/µm at VDS = 0.3 V. The high SS and low Ion comparing to simulation could be resulted from short channel effect, gate misalignment, reduced electric field at tunneling junction due to fringing field, and rough heterojunction interfaces given by a problematic epi. Negative differential resistance at VDS = 0.9 V, and high drain current under reverse drain bias are observed. A heterojunction interface trap-assisted tunneling model is used to explain those behaviors in 3-HJ TFETs.

By scaling semiconductor thicknesses, lithographic dimensions, and contact

resistivities, the bandwidth of InGaAs/InP Hetero-junction Bipolar Transistors

(HBTs) has reached 550/1100 GHz ft/fmax at 128 nm emitter width (wE). Primary challenges faced in scaling the emitter width are: developing high aspect

ratio emitter metal process for wE < 100nm, reducing base contact resistivity

ρb,c, and maintaining high DC current gain β.

The existing W/TiW emitter process for RF HBTs cannot scale below 100

nm. Process modules for scaling the emitter width to 60 nm are demonstrated.

High aspect ratio trenches are etched into a sacrificial Si layer and then filled

with metal via Atomic Layer Deposition (ALD). Metals with high melting points

are chosen to withstand high emitter current densities (JE) at elevated junction

temperatures without suffering from electromigration or thermal decomposition

and is thus manufacturable. ALD deposition of TiN, Pt, and Ru are explored.

Novel base epi designs are proposed for reducing Auger recombination current

(IB,Auger). A dual doping layer in the base is proposed with a higher doping in the

upper 5 nm of the base for lower ρb,c and a lower doping in the remainder of the

base for reducing IB,Auger. Presence of a quasi-electric field (4EC) in the upper

doping grade accelerates electrons away from the region towards the collector,

thus further reducing IB,Auger.

Selective regrowth of the emitter semiconductor via Metal-Organic Chemical

Vapour Deposition (MOCVD) is proposed for decoupling the extrinsic base region

under the base metal from the intrinsic region under the emitter-base junction,

for increasing β,ft, and improving ρb,c. Carbon p-dopants in the InGaAs base are

passivated by H+ during regrowth. Annealing to reactivate carbon induces surface

damage and increases base sheet resistance (Rb,sh) and ρb,c. Process techniques

for minimizing Rb,sh and ρb,c in an emitter regrowth process are demonstrated

and compared. ρb,c of 5.5 Ω.µm2 on p-InGaAs is demonstrated on Transmission

Line Measurement (TLM) structures after regrowth and anneal, by protecting the

semiconductor surface with tungsten. This is comparable to 2.9 Ω.µm2 measured

on TLM structures that do not undergo regrowth and anneal.

Feasibility of emitter regrowth is demonstrated on Large Area Devices (LADs)

with SiO2 as regrowth mask, and W cap during anneal. Emitter-regrowth and

non-regrowth devices of identical dimensions and epi design are compared. Emitterregrown HBTs yield higher β of 28 as compared to 13 for non-regrowth devices.

Benefits of emitter regrowth cannot be ascertained on LADs due to high series

resistance and large gap spacings between base metal and emitter-base junction.

A process flow is proposed for scaling regrown HBTs to 60 nm emitter widths.

The process incorporates ALD emitter metal technology that is demonstrated in

the first half of the dissertation. New epi designs for regrown-emitter HBTs are

optimized for maximizing β, ft. Scaling regrown-emitter HBTs is essential for

realizing their benefit over non-regrowth HBTs.

Because of their wide RF bandwidth (~1 THz) and high breakdown voltages (BV_CEO >3 V), npn-In_0.53Ga_0.47As/InP double heterojunction bipolar transistors (DHBTs) have extensive applications in monolithic microwave integrated circuits (MMICs) such as high performance transceivers, near-terabit optical fiber link, and THz amplifiers in radar/imaging systems. The improvements in the performance of DHBTs were made possible because of device scaling. As the technology advances towards the next scaling generations, new challenges in the manufacturing techniques and the device designs are met. The purpose of this work is to provide solutions to the problems encountered in the fabrication and design of the base-emitter junction while scaling from 200 to sub-100 nm emitter width.

Two important issues regarding the base-emitter junction arises while scaling towards sub-100 nm emitter width. The process flow for the refractory emitter metal stack developed for 250-100 nm emitter width has already reached its limitation. In order to improve the transistor yield at a reduced linewidth without designing a new process flow, revisions have been made to the existing one. Employing the revised process flow, 75 nm-wide emitter is feasible. The overall transistor yield has also been improved. This increases the number of working devices per sample, enabling thorough device analyses.

Experimentally, a reduction of current gain (β) associated with device scaling has been observed. In order to assess the causes of the reduction, the electron transport in the base is emulated by a commercial simulator. A model for DC-β at high injection current density (25 \mA/μm²) was constructed by the comparison between the experimental and the simulation results. The model allows the estimation of β which benefits the design of the future scaling generations of DHBTs.

It has been deduced from the model that the current originated from Auger recombination and lateral electron diffusion (via the surface and the bulk base semiconductor) are the dominant components that limit DC-β. To suppress the diffusion current via surface, a process flow is developed to form passivating sidewall onto the base surface. Such process flow has already been incorporated into DHBT fabrication. Moreover, new geometries for the base-emitter junction have been designed on the purpose of reducing the Auger recombination rate and lateral electron diffusion in the bulk base region. According to the simulation results, the new designs could potentially improve DC-β beyond 50 if the corresponding process flow could be adequately integrated.

This work summarizes the efforts made to extend the current gain cutoff frequency of InP based FET technologies beyond 1 THz. Incorporation of a metal-oxide-semiconductor field effect transistor (MOSFET) at the intrinsic Gate Insulator-Channel interface of a standard high electron mobility transistor (HEMT) has enabled increased gm,i by increasing the gate insulator capacitance density for a given gate current leakage density. Reduction of RS,TLM from 110 Ωμm to 75 Ωμm and Ron(0) from 160 Ωμm to 120 Ωμm was achieved by removing/thinning the wide bandgap modulation doped link regions beneath the highly doped contact layers. Process repeatability was improved by developing a gate metal first process and Dit was improved by inclusion of a post-metal H2 anneal. InxGa1-xAs / InAs composite quantum wells clad with both InP and InxAl1-xAs were developed for high charge density and low sheet resistance to minimize source resistance.

With these improvements a Lg = 8 nm, tch = 6.5 nm transistor with fτ = 511 GHz, fmax = 283 GHz, a Lg = 18 nm, tch = 2.5 nm transistors with fτ = 350 GHz, fmax = 400 GHz, a Lg = 40 nm, tch = 7.0 nm transistor with fτ = 420 GHz, fmax = 592 GHz were demonstrated. Power gain was sometimes limited by RG more than 10 Ω due to poor T-Gate stem filling.

Based on these results and those reported in [1-3], a theory on the effects of channel thickness on quantum well ballistic devices was proposed. Simply, thin quantum wells have large Eigen-state energies limiting the amount of available (EF – E1) beyond threshold.

x

Because a quantum well device’s maximum conductance occurs when EF is equal to or nearly equal to the conduction band minimum of the barrier material, current in thin channel devices is limited not by effective mass effects (i.e. density of states or injection velocity) but by band-offset limitations.