Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales. This dissertation covers challenges and opportunities in identifying variations, their effects and methods to combat these variations for improved microelectronic devices. We focus on timing errors caused by various sources of variations at different levels. We devise methods to mitigate such errors by jointly exposing hardware variations to the software and by exploiting parallel processing. We investigate methods to predict and prevent, detect and correct, and finally conditions under which errors can be accepted. For each of these methods, our work spans defining and measuring the notion of error tolerance at various levels, from ISA to procedures to parallel programs. These measures essentially capture the likelihood of errors and associated cost of error correction at different levels. The result is a design platform that enables us to further combine these methods for a new joint method of detecting and correcting with accepting errors across the hardware/software interface via memoization (i.e., spatial or temporal reuse of computation). We accordingly devise an arsenal of software techniques and microarchitecture optimizations for improving cost and scale of these methods in massively parallel computing units, such as GP-GPUs and clustered many-core accelerators. We find that parallel architectures and parallelism in general provide the best means to combat and exploit variability to design resilient and efficient systems. Using such programmable parallel accelerator architectures, we show how system designers can coordinate propagation of error information and its effects along with new techniques for memoization and memristive associative memory. This discussion naturally leads to use of these techniques into emerging area of "approximate computing", and how these can be used in building resilient and efficient computing systems

Manufacturing and environmental variability lead to timing errors in computing systems that are typically corrected by error detection and correction mechanisms at the circuit level. The cost and speed of recovery can be improved by memoization-based optimization methods that exploit spatial or temporal parallelisms in suitable computing fabrics such as general-purpose graphics processing units (GPGPUs). We propose here a temporal memoization technique for use in floating-point units (FPUs) in GPGPUs that uses value locality inside data-parallel programs. The technique recalls (memorizes) the context of error-free execution of an instruction on a FPU. Therefore, it avoids redundant execution and saves energy for FPU. To enable scalable and independent recovery, a single-cycle lookup table (LUT) is tightly coupled to every FPU to maintain contexts of recent error-free executions. The LUT reuses these memorized contexts to exactly, or approximately, correct errant FP instructions based on application needs. In real-world applications, the temporal memoization technique achieves an average energy saving of 13%{25% for a wide range of timing error rates (0%{4%) and outperforms recent advances in resilient architectures. This technique also enhances robustness in the voltage overscaling regime and achieves relative average energy saving of 44% with 11% voltage overscaling.

Pre-2018 CSE ID: CS2014-1006

Variation in performance and power across manufactured parts and their operating conditions is an accepted reality in aggressive CMOS processes. This paper considers challenges and opportunities in identifying this variation and methods to combat or even use these variations for improved computing systems. We introduce the notion of instruction-level vulnerability (ILV) and concurrent instruction reuse (CIR) to expose variation and its effects to the software stack for use in architectural and runtime optimizations. Going further up on the hardware-software stack, we also introduce the notion of tasklevel vulnerability (TLV) as metadata to characterize dynamic variations. In fact, TLV is a vertical abstraction that reflects manifestation of circuit-level hardware variability in specific software context for parallel execution model.

Pre-2018 CSE ID: CS2014-1004

Objective

The purpose of this study was to investigate the intra-rater reliability and validity of a designed load cell setup for the measurement of back extensor muscle force and endurance.

Participants

The study sample included 19 older women with hyperkyphosis, mean age 67.0 ± 5.0 years, and 14 older women without hyperkyphosis, mean age 63.0 ± 6.0 years.

Methods

Maximum back extensor force and endurance were measured in a sitting position with a designed load cell setup. Tests were performed by the same examiner on two separate days within a 72-hour interval. The intra-rater reliability of the measurements was analyzed using intraclass correlation coefficient (ICC), standard errors of measurement (SEM), and minimal detectable change (MDC). The validity of the setup was determined using Pearson correlation analysis and independent t-test.

Results

Using our designed load cell, the values of ICC indicated very high reliability of force measurement (hyperkyphosis group: 0.96, normal group: 0.97) and high reliability of endurance measurement (hyperkyphosis group: 0.82, normal group: 0.89). For all tests, the values of SEM and MDC were low in both groups. A significant correlation between two documented forces (load cell force and target force) and significant differences in the muscle force and endurance among the two groups were found.

Conclusion

The measurements of static back muscle force and endurance are reliable and valid with our designed setup in older women with and without hyperkyphosis.

Objective

The purpose of this study was to investigate the intra-rater reliability and validity of a designed load cell setup for the measurement of back extensor muscle force and endurance.

Participants

The study sample included 19 older women with hyperkyphosis, mean age 67.0 ± 5.0 years, and 14 older women without hyperkyphosis, mean age 63.0 ± 6.0 years.

Methods

Maximum back extensor force and endurance were measured in a sitting position with a designed load cell setup. Tests were performed by the same examiner on two separate days within a 72-hour interval. The intra-rater reliability of the measurements was analyzed using intraclass correlation coefficient (ICC), standard errors of measurement (SEM), and minimal detectable change (MDC). The validity of the setup was determined using Pearson correlation analysis and independent t-test.

Results

Using our designed load cell, the values of ICC indicated very high reliability of force measurement (hyperkyphosis group: 0.96, normal group: 0.97) and high reliability of endurance measurement (hyperkyphosis group: 0.82, normal group: 0.89). For all tests, the values of SEM and MDC were low in both groups. A significant correlation between two documented forces (load cell force and target force) and significant differences in the muscle force and endurance among the two groups were found.

Conclusion

The measurements of static back muscle force and endurance are reliable and valid with our designed setup in older women with and without hyperkyphosis.

OBJECTIVE:The purpose of this study was to investigate the intrarater reliability of a skin-surface instrument (Spinal Mouse, Idiag, Voletswil, Switzerland) in measuring standing sagittal curvature and global mobility of the spine in older women with and without hyperkyphosis. METHODS:Measurements were made in 19 women with hyperkyphosis (thoracic kyphosis angle ≥50°), mean age 67 ± 5 years, and 14 women without hyperkyphosis (thoracic kyphosis angle <50°), mean age 63 ± 6 years. Sagittal thoracic and lumbar curvature and mobility of the spine were assessed with the Spinal Mouse during neutral standing, full spinal flexion, and full spinal extension. Tests were performed by the same examiner on 2 days with a 72-hour interval. The intrarater reliability of the measurements was analyzed using the intraclass correlation coefficient, standard error of measurement and minimal detectable change. RESULTS:Intraclass correlation coefficients ranged from 0.89 to 0.99 in both groups. The standard errors of measurement ranged from 1.02° to 2.06° in the hyperkyphosis group and from 1.15° to 2.22° in the normal group. The minimal detectable change ranged from 2.85° to 5.73° in the hyperkyphosis group and from 3.20° to 6.17° in the normal group. CONCLUSIONS:Our results indicated that the Spinal Mouse has excellent intrarater reliability for the measurement of sagittal thoracic and lumbar curvature and mobility of the spine in older women.

This article reviews recent progress in the development of the computing framework Vector Symbolic Architectures (also known as Hyperdimensional Computing). This framework is well suited for implementation in stochastic, emerging hardware and it naturally expresses the types of cognitive operations required for Artificial Intelligence (AI). We demonstrate in this article that the field-like algebraic structure of Vector Symbolic Architectures offers simple but powerful operations on high-dimensional vectors that can support all data structures and manipulations relevant to modern computing. In addition, we illustrate the distinguishing feature of Vector Symbolic Architectures, computing in superposition, which sets it apart from conventional computing. It also opens the door to efficient solutions to the difficult combinatorial search problems inherent in AI applications. We sketch ways of demonstrating that Vector Symbolic Architectures are computationally universal. We see them acting as a framework for computing with distributed representations that can play a role of an abstraction layer for emerging computing hardware. This article serves as a reference for computer architects by illustrating the philosophy behind Vector Symbolic Architectures, techniques of distributed computing with them, and their relevance to emerging computing hardware, such as neuromorphic computing.