Behavioral synthesis that takes into consideration real components as well as timing constraints is necessary for the design of today's ASIC chips. In this report, we give a methodology for design space exploration under timing constraints. To illustrate our proposed methodology, we also give several designs that implement a Square Root Algorithm. We compare these designs and give their behavioral and structural description in the Appendix.

Fourier transform techniques are very popular and practical for DSP applications. Among them, Discrete Fourier Transform (DFT) and its fast algorithm (FFT) are best known and most important. In this report, we define two general communication models and a corresponding handshaking protocol for the FFT chip. We explore multiple design alternatives using efficient pipelining techniques, and show what algorithm transformations are needed. From this example we derive a methodology for applying the pipelining techniques in a time-constrained formulation. Parameterization for a more general ITT chip is also discussed.

ASICs for video compression systems have stringent timing requirements. For example, according to the MPEG standard, the throughput of the MPEG decoder is 30 frames per second. This performance cannot be achieved without efficient pipelining. In this report, we explore the pipelined designs for the Inverse Discrete Cosine Transform (IDCT) which is a critical part of the MPEG decoder. We also transform the algorithm to minimize the memory requirement. We have implemented both the original and memory-optimized algorithms at the RT level, using our realistic library.