In this thesis, the PLL design for FMCW radar systems is illustrated. The FMCW radar imposes requirements on the PLL-based chirp generator in several aspects. Both the phase noise and the bandwidth of the PLL influence the measurement accuracy and resolution of the radar. The phase noise should be minimized, given a certain power consumption, and the bandwidth needs to be matched with the FMCW chirp slope to achieve better linearity.

For system-level design, unlike PLLs for other applications, the output of the chirp generator PLL is always changing. In many applications, such as precision measurement, the output never truly settles at each step. This necessitates careful modeling of the loop dynamics. In this thesis, conventional PLL phase noise and settling time models are presented and adapted for the chirp generator. However, these models are insufficient for optimizing the design. Therefore, a more accurate time-domain model for calculating the chirp is proposed. This model aids in designing the PLL bandwidth, calculating the acceptable chirp slope for a given PLL, and computing the dynamic phase noise. To the best of our knowledge, this is the first relatively accurate model for the entire chirp generation process.

For the design of circuit blocks, the frequency division modules, which include a dualmodulus divider and a Delta-Sigma Modulator, are presented. For the high-frequency circuit, an analytical model and a corresponding design methodology are proposed. The PLL has been taped-out, and measurements will be conducted to confirm the performance and design methodology.