Flash-based storage drives such as solid-state disks are replacing traditional spinning disk drives for an increasing number of applications. User interfacing cloud-based applications benefit from the low, sub-millisecond access latency of solid-state drives (SSDs). Virtually all smartphones are using flash memory as their storage media due to features such as low power consumption, larger storage density, small footprint, and shock resistance. SSDs provide faster boot times, higher read and write bandwidth as well as improved durability. Nevertheless, flash-based storage devices show several disadvantages. Technology scaling, 3D integration as well as multi-level bit cells have continuously increased storage density and capacity, however, this has also reduced the reliability of flash. Flash memory also suffers from overheads such as garbage collection, which can reduce write bandwidth and introduce high tail latency. Furthermore, while NAND flash devices provide significantly lower latency than spinning disks, flash has still orders of magnitude higher latency than DRAM.

This work leverages machine learning techniques to improve the performance of flash-based storage systems. This improvement reflects in three major directions - improving response time, reliability, and lifetime of flash-based storage devices. For improving response time, we leverage sequence-to-sequence machine learning techniques to learn the spatial IO access patterns thereby improving prefetching performance. To achieve high performance, we address the challenges of prefetching in very large sparse address spaces, as well as prefetching in a timely manner by predicting ahead of time. To improve reliability, we propose an approach of automatically predicting and interpreting future drive failures. Finally, we present a machine learning based approach for reducing the number of rewrites required to store data in log-structured file systems via death-time prediction of logical block addresses. We leverage the predicted death-times in designing \sysML, a near-optimal data placement technique that minimizes the number of extra writes required to store data in log-structured storage systems thereby improving device lifetime.

In this thesis, I introduce the SmartSSD architecture and list the hardware and software requirements for the system. Then I give a brief overview of the domain of genomics and discuss suitability for this architecture. I then evaluate two workloads and profile them for amenability for this architecture. In this process, I provide key insights that aid in the process and develop a methodology for the using and

developing on this system.

Translating the computation-critical part of an application to special-purpose hardware is a standard practice to achieve performance gain and speed-up in execution time. In this thesis, we chose a gene sequence aligner tool: Minimap2 as a workload. This thesis implements the kernel of Minimap2 in hardware using Verilog and parameterizes the design to support parallelism. We subsequently evaluate the design’s performance on timing, speed-up, and area utilization.

he Von Neumann bottleneck is a persistent problem in computer architecture, causing stalls and wasted CPU cycles. The Von Neumann bottleneck isparticularly relevant for memory-intensive workloads whose working set does not fit into the microprocessor’s cache and hence memory accesses suffer the high access latency of DRAM. One technique to address this bottleneck is to prefetch data from memory into on-chip caches. While prefetching has proven successful, for simple access patterns such as strides, existing prefetchers are incapable of providing benefit for applications with complex, irregular access patterns. A neural network-based prefetcher shows promise for these challenging workloads. We provide an understanding of what type of memory access patterns an LSTM neural network can learn by studying its effectiveness on a suite of microbenchmarks with well-characterized memory access patterns, and perform a parameter sensitivity analysis to identify the most important model parameters. We achieve over 95% accuracy on the microbenchmarks and find a strong relationship between lookback (history window) size and the ability of the model to learn the pattern. We find also an upper limit on the number of concurrent distinct memory access streams that can be learned by a model of a given size.