Doped-multilayer-graphene (DMLG) interconnects employing the subtractive-etching (SE) process have opened a new pathway for designing interconnects at advanced technology nodes, where conventional metal wires suffer from significant resistance increase, self-heating (SH), electromigration (EM), and various integration challenges. Even though single-level scaled graphene wires have been shown to possess better performance and reliability with respect to dual-damascene (DD) and SE-enabled metal wires, a multi-level graphene interconnect technology (with vias) has remained elusive, which is of paramount importance for its integration in future technology nodes. This work, for the first time, addresses that need by engineering a CMOS-compatible solid-phase growth technique to yield large-area multilayer graphene (MLG) on dielectric (SiO2) and metal (Cu) substrates and subsequently demonstrating multi-level MLG interconnects with metal vias. Using rigorous theoretical and experimental analyses, we demonstrate that multi-level MLG interconnects with metal vias undergo < 2% change in the via resistance under accelerated stress conditions, demonstrating its superior reliability against SH and EM, making them ideal candidates for sub-10 nm nodes.

Since the discovery of graphene in 2004, which proved the existence of 2-D crystals in nature, layered materials also known as van der Waals solids have received extensive reexamination, especially in the single-layer and multilayer forms because of their van der Waals type structure and unique properties that not only benefit many existing electronic components but also enable novel device concepts and design architectures. Numerous research efforts have been invested in these materials, and enormous quantities of results have been generated during the past 14 years. This paper provides an overview of the key physics and technology issues along with the most promising nanoelectronic applications of these materials and also identifies the challenges in this rapidly evolving field.

Brain-like energy-efficient computing has remained elusive for neuromorphic (NM) circuits and hardware platform implementations despite decades of research. In this work we reveal the opportunity to significantly improve the energy efficiency of digital neuromorphic hardware by introducing NM circuits employing two-dimensional (2D) transition metal dichalcogenide (TMD) layered channel material-based tunnel-field-effect transistors (TFETs). Our novel leaky-integrate-fire (LIF) based digital NM circuit along with its Hebbian learning circuitry operates at a wide range of supply voltages, frequencies, and activity factors, enabling two orders of magnitude higher energy-efficient computing that is difficult to achieve with conventional material and/or device platforms, specifically the silicon-based 7 nm low-standby-power FinFET technology. Our innovative 2D-TFET based NM circuit paves the way toward brain-like energy-efficient computing that can unleash major transformations in future AI and data analytics platforms.

Copper-based interconnects employed in a wide range of integrated circuit (IC) products are fast approaching a dead-end due to their increasing resistivity and diminishing current carrying capacity with scaling, which severely degrades both performance and reliability. Here we demonstrate chemical vapor deposition-synthesized and intercalation-doped multilayer-graphene-nanoribbons (ML-GNRs) with better performance (more than 20% improvement in estimated delay per unit length), 25%/72% energy efficiency improvement at local/global level, and superior reliability w.r.t. Cu for the first time, for dimensions (down to 20 nm width and thickness of 12 nm) suitable for IC interconnects. This is achieved through a combination of GNR interconnect design optimization, high-quality ML-GNR synthesis with precisely controlled number of layers, and effective FeCl₃ intercalation doping. We also demonstrate that our intercalation doping is stable at room temperature and that the doped ML-GNRs exhibit a unique width-dependent doping effect due to increasingly efficient FeCl₃ diffusion in scaled ML-GNRs, thereby indicating that our doped ML-GNRs will outperform Cu even for sub-20 nm widths. Finally, reliability assessment conducted under accelerated stress conditions (temperature and current density) established that highly scaled intercalated ML-GNRs can carry over 2 × 10⁸ A/cm² of current densities, whereas Cu interconnects suffer from immediate breakdown under the same stress conditions and thereby addresses the key criterion of current carrying capacity necessary for an alternative interconnect material. Our comprehensive demonstration of highly reliable intercalation-doped ML-GNRs paves the way for graphene as the next-generation interconnect material for a variety of semiconductor technologies and applications.