In this paper, we present a probabilistic algorithm for analyzing cost/performance tradeoffs in interactive synthesis of DSP algorithms. Our approach is based on an analysis of data dependencies combined with a probabilistic scheduling technique in which operations are iteratively redistributed to minimize resource cost. Our algorithm may consider both memories with different access times and pipelined units with different numbers of stages. The output is a shape function illustrating the cost vs. performance tradeoff. We have tested this algorithm on several benchmarks including an FIR filter, a linear recurrence solver, and a robot kinematics example. Results show that the average error in cost, as compared to manual designs, is 0.41 %, while the average error in performance is 4.90 % without memory access times and 0.77 % with memory access times. The maximum cost (performance) error generated by our algorithm on our benchmarks is 5 % (22 %).

In this report we describe the design process for behavioral synthesis from VHDL descriptions. The design process can be divided into two parts, (a) the architectural allocator (AA), which derives the appropriate type and number of resources (storage, functional units, and buses) that can satisfy the area and performance constraints imposed by the designer, and (b) the VHDL SynthesisSystem (VSS), which synthesizes a RT-level netlist based on the allocation constraints. The human interface for all the tasks in the design process is also described in this report.

In this report, we present a top-down VHDL modeling technique which consists of two main modeling levels: specification level and functional level. We modeled a RISC Processor (RP) in order to demonstrate the feasibility and effectiveness of this methodology. All models have been simulated on a SPARC 1 workstation using the ZYCAD VHDL simulator, version 1.0a. Experimental results show feasibilty of the modeling strategy and provide performance measures of RP design features.