Recursive decoding techniques are considered for Reed-Muller (RM) codes of growing length n and fixed order r. An algorithm is designed that has complexity of order n log n and corrects most error patterns of weight up to n(1/2 - epsilon) given that epsilon exceeds n^{-1/2^r}. This improves the asymptotic bounds known for decoding RM codes with nonexponential complexity. To evaluate decoding capability, we develop a probabilistic technique that disintegrates decoding into a sequence of recursive steps. Although dependent, subsequent outputs can be tightly evaluated under the assumption that all preceding decodings are correct. In turn, this allows us to employ second-order analysis and find the error weights for which the decoding error probability vanishes on the entire sequence of decoding steps as the code length n grows.

Reed-Muller (RM) codes are classical codes that have enjoyed unabated interest since their introduction in 1954 due to their simple recursive structure and low-complexity decoding. The main goal of the thesis is to develop new coding techniques that can improve the performance of RM codes. In this work, we wish to keep the recursive low-complexity structure of RM codes while extending the sets of possible parameters and decoding algorithms. We address this task using two different methods. First, we consider new code constructions that extend code parameters using puncturing. Second, we design new decoding algorithms that repeatedly use the gradient properties of the classic recursive structure to improve code performance of RM codes.

In the first part of the thesis, we propose a new class of codes that enjoy the recursive structure of RM codes, but reduce the exponential length of RM codes to a polynomial in m. These codes are obtained by puncturing classical RM codes, i.e. by restricting binary RM codes to small subsets of their positions. We study new recursive properties of these codes and analyze their parameters.

In the second part of the thesis we develop new decoding algorithms for binary RM codes of second order that achieve near optimal performance for short and moderate code lengths. RM codes enjoy some simple decoding procedures; however, these algorithms fall short of optimal performance on moderate block lengths. We propose a suboptimal algorithm that reduces the complexity of maximum-likelihood decoding from super-polynomial order O(n^(m+1)/2) to polynomial order O(mn²). At the same time, our numerical simulations show that the new algorithm performs very closely to its maximum-likelihood counterpart for blocks of up to several thousand bits.

Low latency and low power communications have broad applications such as Internet of things (IoT), autonomous vehicles, industry automation (collaborative robots), health procedures (like robot assisted surgery requiring haptic feedback), satellite communication, radar applications, virtual reality headsets and millimeter Waves (mmWave).Low latency communications is in high demand for autonomous systems to be able to react swiftly to changes in the environment and to unexpected situations. Latency is tied to the technology used and even more to the overall architecture adopted. Enhanced mobile broadband, massive machine type communications and ultra-reliable and low latency communication are the most prominent promises of 5th generation mobile network (5G). The low power wide area networks communications is expected to grow exponentially from the 1.5B\$ of 2018 to 65B\$ in 2025 and communication services, asset tracking and smart buildings (installation and operation) are just some of its applications. Low power communications can use a number of different protocols and systems like Narrow-band (NB) IoT and Long Range Wide Area Network (LoRaWAN). Long range wide area networks use unlicensed spectrum and are more suitable for applications generated in low traffic volume (which is typically the case for IoT). All these applications of low power and low latency communication were the motivation behind our research.

In this thesis, we introduce a low-rate low-density parity-check (LDPC) code for channels with extreme noise and present a low latency and low complexity communication method for low power applications. We then show that this design has the ability of outperforming uncoded modulation for the signal-to-noise ratios (SNR) above $-3$ dB per information bit and achieve a $3$ dB gain as SNR grows.We use belief propagation (BP) decoding only on information bits to decode these codes and by doing so the overall complexity of decoding would be log-linear in terms of block size. To improve code performance, information bits are further protected with a polar code. The combined design has low complexity of decoding, small latency and a vanishing bit error rate (BER).

We also prove upper and lower bounds on bit error rate of these algorithms at any SNR and study a combined scheme that splits the information block into $b$ blocks and protects each with some polar code.Decoding moves back and forth between polar and LDPC codes, every time using a polar code of a higher rate. For a sufficiently large constant $b$ and a large block size, this design yields a vanishing BER at any SNR that is arbitrarily close to the Shannon limit of -1.59 dB. This scheme also has very low complexity and decodes $m$ information bits with complexity of order $\mathcal{O}(m\log m)$ per information bit.

In the subsequent chapters of this thesis, we combine polar and low-density parity-check (LDPC) with parity checks of small weight to achieve low latency and low complexity codes for high noise channels. Decoding of this codes also performs several iterations of the belief propagation (BP) algorithm.Partially corrected bits are then passed to a short polar code that uses successive cancellation list (SCL) decoder. The newly corrected bits then serve as the new inputs for the LDPC decoder. For codes of rate less than 0.05, the algorithm performs on a par with a cyclic redundancy check (CRC) aided successive cancellation list (CA-SCL) decoder, while substantially reducing its latency.

In the past decades, semiconductor industry has been enhancing the performance of silicon-based processor through downsizing the size of transistors. However, miniaturization is approaching the physical limits. Difficulties like floating gate interference, low coupling ratio, and heat dissipation are increasingly severe. Therefore, nanoscale magnetic logic system, as a prominent alternative technology, is being studied.

A theoretical study is reported to use a patterned network of nanomagnets (nanocells) as a new architecture for next-generation computing processors, in which the direction of the magnetization represents a binary signal in each cell.

Such shape-insensitive nanomagnetic devices can relieve severe fabrication constraints associated with building nanomagnetic cells of narrowly defined shapes. Particularly, comparison between materials with in-plane and out-of-plane crystalline anisotropy is presented. Properties of materials with in-plane crystalline anisotropy can be tailored to match those of shape-induced longitudinal nanomagnets while materials with out-of-plane anisotropy could enable a new set of features. For instance, besides the key features of any magnetic logic, i.e., non-volatility, low-power consumption, and radiation hardness, some of the new features of the out-of-plane materials include (i) cost-effective fabrication, (ii) scalability to sub-10-nm dimensions, and (iii) their natural ability to be extended into a three-dimensional (3-D) physical space which opens a new era of technology opportunities.

Implementation of a high density three-layer magnetic recording device is introduced. It proves the feasibility of using multilayer nanomagnetic material with perpendicular anisotropy to store 2N levels of signal (N is the amount of magnetic layers). Related experimental results are demonstrated. Moreover, similar three-dimensional four-layer architecture is proven to be a potential candidate of building majority logic gates.

Development of energy-efficient spin-transfer torque (STT) magnetization reversal in sub-10nm magnetic tunneling junction (MTJ) point contacts is also explored. Reducing required switching current of STT-MTJ is an essential and practical issue in the manufacturing industry of STT-based MRAM. Both simulation and experimental results show the switching current requirement is at least an order magnitude less in devices of length in sub-10nm region, which has great importance for developing next generation MRAM. Besides, experimental results show there is little relevance between contact resistance and the TMR effect amplitude.

In recent years, current data storage and semiconductors have begun to reach their fundamental limits. In current hard disk drive based data storage technology the size of the magnetic bit that data is stored on has begun to reach it size limits due to the superparamagnetic limit. In semiconductor technologies, devices are beginning to reach their fundamental limits due to the current leakage effect in small devices. If these technologies will continue with the current trends of packing more data/devices into the same area, new technologies need to be developed. In the following pages, two new technologies will be proposed for increasing the areal density of magnetic data storage technologies. After that, three novel approaches to creating logic cells on patterned magnetic media at much higher areal densities than current semiconductor technologies can support. First a study of Co/Pd multilayers as a candidate material for the next generation of magnetic media for a number of applications will be described. Following that, a patterned, three layer, magnetic media made up of magnetic multilayers will be fabricated and tested to show the feasibility of using it for the basis of next generation data storage technologies. Then, three novel approaches to magnetic logic gates using magnetic multilayers based media will be designed, fabricated, and tested using state of the art fabrication and analysis techniques. Each of the proposed magnetic logic cells will consist of a patterned media made up on of two, three, or four stacked magnetic multilayers media. The two layer structures are fabricated to be implemented on current hard disk drives. The three and four stacked structures can be implemented in a number of ways, from hard disk drives to magnetic quantum-dot cellular automata. The latter would allow these logic cells to be integrated with semiconductor technologies to create a hybrid device that utilizes the best aspects of each technology.

This dissertation is designed to focus on the field of nonlinear impairments generated along the fiber-optic transmission links in high spectral efficiency optical modulation systems, while also extracting the performance trade-offs of conventional and novel receivers. Fundamental knowledge of optical fiber, major phase modulation nonlinearities, and high spectral efficiency optical modulation and reception are discussed on an introductory level. Further, balanced detection schemes for optical duobinary with a comparison of differential phase shift keying (DPSK) are demonstrated and analyzed, both in simulations and experiments. Frequency discriminator receiver structures for quadrature phase shift keying (QPSK) as well as their linear and nonlinear noise properties are exhibited. At the end, polarization multiplexing QPSK with digital coherent receiver well known as future vision of fiber-optic communications is also simulatedly studied through the RZ- and NRZ- pulse shape impact in a 9-channel 100G wavelength division multiplexing (WDM) systems.

Quantum decoherence and errors represent some of the major challenges arising in quantum computations. Quantum error correcting codes protect quantum states against these errors and make quantum computing more reliable. One of the main problems of quantum error correction is the design of feasible decoding algorithms that can simplify error-correction for general quantum codes. The dissertation addresses decoding of general Codeword Stabilized (CWS) codes. This class of quantum codes also includes some other important classes such as additive Stabilizer codes and non-additive Union Stabilizer (USt) codes.

We first design a generic error-correcting algorithm for CWS codes and analyze the number of decoding measurements and quantum gates. This algorithm performs exhaustive screening of different error patterns, similar to decoding of classical non-linear codes. For an n-qubit quantum code correcting up to t erroneous qubits, this brute-force approach consecutively tests all correctable error patterns and employs a separate n-qubit measurement in each test.

The main result is a new error grouping technique that enables simultaneous testing of large groups of errors in a single measurement. To achieve this reduction, we first proceed with a new error-correction algorithm for the USt codes. Secondly, we design an algorithm that converts generic non-linear CWS codes into the simpler quasi-linear USt codes. Each decoding measurement can then either locate the actual error in a given group of errors or entirely eliminate this group. This technique yields a much simpler algorithm that exponentially reduces the number of measurements about 3^t times in any t-error-correcting CWS code.