High temperatures and large thermal variations on the die create severe challenges in system reliability, performance, leakage power, and cooling costs. Designing for worst-case thermal conditions is highly costly and time-consuming. Therefore, dynamic thermal management methods are needed to maintain safe temperature levels during execution. Conventional management techniques sacrifice performance to control temperature and only consider the hot spots, neglecting the effects of thermal variations. This thesis focuses on developing performance- efficient techniques to achieve safe and balanced thermal profiles on multiprocessor system-on-chips (MPSoCs). Modeling performance, temperature, and reliability of MPSoCs with high accuracy and reasonable simulation time is a challenge, because we need to keep track of instruction-level activities and also simulate sufficiently long real-time execution to have meaningful reliability estimates. The first contribution of this thesis is a fast simulation framework, which evaluates reliability of runtime policies or design-time decisions accurately in a matter of hours--whereas traditional architecture-level simulators would have to run for days. Job scheduling on an MPSoC has a significant impact on temperature and reliability. For systems with a priori known workloads, this thesis proposes a scheduling optimization method which outperforms other static energy or temperature management techniques in terms of reducing thermal hot spots and gradients. However, having an accurate design-time workload estimate is not possible for most systems. This work introduces dynamic techniques to address runtime variations in workload. The key aspects of these dynamic techniques are low-performance impact and adaptation capability. Reacting after thermal events occur reduces the efficiency of thermal management policies. This thesis proposes a novel proactive management approach to address this issue, and shows that utilizing a thermal forecast for temperature-aware scheduling achieves significant gains in both temperature and performance. All the novel management policies introduced in this thesis are evaluated using an experimental framework based on real-life systems and workloads. In the experiments on an UltraSPARC T1 processor, proactive thermal management achieves remarkable results with an average 60% reduction in hot spot occurrences, 80% reduction in spatial gradients and 75% reduction in thermal cycles in comparison to reactive thermal management, while also improving performance

Future microprocessors will be highly susceptible to transient errors as the sizes of transistors decrease due to CMOS scaling. Prior techniques advocated full scale structural or temporal redundancy to achieve fault tolerance. Though they can provide complete fault coverage, they incur significant area and/or performance overhead. It is desirable to have a mechanism that can provide, incomplete, but still sufficiently high fault coverage with negligible area and/or performance cost. To achieve this goal, in this paper, we examine exploiting speculative structures that already exist in modern processors to provide partial fault coverage. We start by quantifying how much the faulty program deviates from the correct program execution in terms of control flow, address patterns and store values. We find this classification useful to design techniques that can detect a particular form of deviation and thereby ultimately detect the transient fault. In order to detect transient faults, we propose augmenting branch predictors to detect control flow errors, store sets and L2 cache misses to predict faults that might have resulted in incorrect address references, and a value predictor to detect incorrect store values.

Pre-2018 CSE ID: CS2005-0847

We introduce a Force-directed List Scheduling (FDLS) algorithm for resource-constrained assay compilation targeting Digital Microfluidic Biochips (DMFBs). This algorithm has been used in the past for high-level synthesis of digital signal processing systems, and is now applied to DMFB synthesis. The results show improvements compared to List Scheduling (LS) and Path Scheduling (PS), the most efficient heuristics that have been proposed, to date, for DMFBs. FDLS was also competitive with longer-running iterative improvement DMFB scheduling algorithms based on genetic algorithms. © 2012 IEEE.

Synthesis of digital microfluidic biochips (DMFBs) is a crucial to the advancement and realization of miniaturized, automated, programmable biochemistry solutions; synthesis is performed in three steps: scheduling, placement and routing. In principle, algorithms for specific steps should be interchangeable with one another; however, different research groups typically develop algorithms for each step in isolation from one another. Thus, it is difficult to compare algorithms against one another, or to determine which algorithms for different steps share synergies. We introduce an open source DMFB synthesis framework to encourage collaboration between researchers working in the area. We introduce a common interface and describe the internal data structures that must be updated to ensure that the interfaces are adhered to. We also present and describe a number of high-quality 2D and 3D debugging tools that provide graphical output for each stage of synthesis. © 2012 IEEE.

HIV +Elite and Viremic controllers (EC/VCs) are able to control virus infection, perhaps because of host genetic determinants. We identified 16% (21 of 131) EC/VCs with CD4 +T cells with resistance specific to R5-tropic HIV, reversed after introduction of ccr5. R5 resistance was not observed in macrophages and depended upon the method of T cell activation. CD4 +T cells of these EC/VCs had lower ccr2 and ccr5 RNA levels, reduced CCR2 and CCR5 cell-surface expression, and decreased levels of secreted chemokines. T cells had no changes in chemokine receptor mRNA half-life but instead had lower levels of active transcription of ccr2 and ccr5, despite having more accessible chromatin by ATAC-seq. Other nearby genes were also down-regulated, over a region of ~500 kb on chromosome 3p21. This same R5 resistance phenotype was observed in family members of an index VC, also associated with ccr2/ccr5 down-regulation, suggesting that the phenotype is heritable.