As fabrication technology improves, computation ability has increased accordingly and enables new applications such as biomedical and health monitoring system, internet of things (IoT) and home security surveillance. To satisfy stringent requirements such as limited supply, power and area for these new specs of emerging applications, critical circuit blocks must operate under low supply voltage and if possible generate power from ambient environments. Besides, these new applications can be further popularized if costly off-chip passive components which occupies large PCB footprint can be avoided.

This thesis firstly introduces fundamentals of phase locked loop (PLL) which provides clock to all analog and digital circuits in systems. Then a 0.75V 0.014mm2 2.6GHz digital bang-bang PLL with dynamic double-tail phase detector and supply-noise-tolerant gm-controlled DCO is proposed. At last, this thesis introduces a fully integrated CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mV startup voltage. Both circuits adopt no off-chip devices and can operate under low voltage or harvest energy from ambient environments. The prototype DBBPLL has been implemented in a mainstream 28nm CMOS process and consumes 2.9mW at the same time achieves low in-band phase noise of -105dBc/Hz. The energy harvester is implemented in 28nm CMOS, it achieves a self-startup voltage of 110mV without RF input and 85mV at -16dBm input. The boost converter power conversion efficiency (PCE) is 25% and the harvester overall PCE is 10%.

Autonomous driving of vehicles has been becoming a reality and radar is an indispensable feature of this transportation method. However, there will be interference issues due to the multiple signals transmitted from the radars on the adjacent driving vehicles operating in the same area at the same time. Consequently, radar interference mitigation techniques will be essential in such multi-vehicle environment. In order to accurately detect and localize adjacent vehicles, several radars must be carried on each vehicle. A low-cost and highly-integrated CMOS radar sensor could be the best candidate to fulfill this growing industrial need.

Linear frequency-modulated continuous-wave (FMCW) radar with constant envelope

waveform is suitable for low-power/ low-cost CMOS implementation. However, the ghost

targets due to other radars and radio interference generate false alarms and lower the probability of detection. Some interference mitigation techniques allocating frequency sub-bands at different time for different users to avoid concurrent frequency band usage have been proposed in the past. However, the number of users must trade off with the available bandwidth so does the range resolution.

This dissertation presents an interference-tolerant radar which can endure multiple signals transmitted from adjacent vehicles for autonomous driving applications. The interference immunity property has been realized by applying a specific code-division multiplexing method, involved with one-coincidence frequency hopping code, to the continuous-wave radar. A radar prototype has been implemented in 65nm CMOS for operation at 24GHz with 1GHz bandwidth (equivalently with 15cm range resolution). Measurements indicate that the prototype can support up to 22 adjacent vehicles simultaneously by using the optimized Hamming correlation property of the extended hyperbolic congruential code.

A 60GHz band LNA in 65nm CMOS technology is presented in this paper with minimum noise figure of 3.6dB and maximum DC power dissipation of 8.5mW. This LNA operates in -3dB fractional bandwidth of over 20% with maximum voltage gain and noise variations of 1.64dB and 0.3dB, respectively, over the whole band of operation.

In today's System–on–Chip (SoC) design, both analog and digital circuits play important role. Digital circuits are fully used to build memory and signal processing blocks. With technology scaling, speed of digital circuits has been boosted a lot in deep submicron technologies. Being the interface between real world and digital block, Analog–to–Digital Converter (ADC) is now very critical. Since high speed and high precision is required, ADC has now become a bottleneck in SoC design. Especially when integrated with digital circuits, ADC has to maintain its performance in noisy environment. Therefore, effort is deserved to develop high resolution, low power ADC designs. In this thesis, an 11–bit Pipelined ADC with Op Amp sharing technique is presented. The post–layout simulation shows an SNDR of 59.46dB and SFDR of 69.00dB. Current consumption is around 11mA from 2.5V power supply.

Accompanying and enabling the explosion of information technology in the recent decades, RF CMOS design has grown into a mature discipline and a multi-billion industry, and CMOS radio transceivers can be found in almost every consumer electronic devices nowadays. To enable the next generation RF CMOS applications, advances in both system and circuit techniques need to be accomplished. This work presents several of these advances, specifically in the context of the data communication application and low noise circuit techniques.

First, a new wideband receiver architecture suitable for wireless communication is proposed and analyzed. The architecture has both phase and thermal noise cancellations to significantly relax the trade-offs between VCO phase noise and LOGEN power consumption, and trade-offs between noise, out-of-band linearity, and wide input bandwidth.

Next, a current-mode mm-wave receiver architecture is described. The mm-wave receiver relies on current mode operation and novel techniques in passive devices to achieve wide RF bandwidth, low noise, and high out-of-channel linearity. It considers mm-wave receivers' adjacent/alternative channel blocking scenarios for the first time.

Finally, a high speed on-chip RF-Interconnect with quarter-wavelength directional coupler for bi-direction communication and multi-drop arbitration is presented. The proposed system introduces an emerging on-chip interconnect solution with superior latency and power efficiency. It also brings tremendous flexibility and re-configurability, which proves to be extremely beneficial to the next generation large scale Network-on-Chip (NoC) system.

Digital circuits implemented in CMOS technology have been the workhorses of high performance computer processors for more than a decade, following Moore's law with exponentially increasing integration and performance. Driven by lower cost, increasing performance, and mixed-signal benefits, CMOS technology also has found increasing use in analog, and more recently, RF applications. Now, with transistor performance still improving, wires are becoming the limiting factor for speed and performance by imposing limits on communication bandwidth and latency between processing cores and memories, both off-and on-chip. Communication and circuit techniques, developed mainly for narrow band-wireless RF communication can help increase the wired communication speed in digital systems. This approach, dubbed RF Interconnect (RF-I), picks up speed for on-board and on-chip applications, changing the communication paradigm from the old parallel unidirectional time-shared bus to new transmission lines enabling reconfigurable communication using both frequency and code division multiple access techniques.

Touch sensing has been widely implemented as a main methodology to bridge human and machine interactions. The traditional touch sensing range is two dimensional and therefore limits the user experience. The required physical contact inherent of the technology creates several disadvantages, including unresponsiveness due to wet fingers, and unavoidable fingerprint residue on the screen surface.

To overcome these limitations, we propose a novel 3D contactless touch sensing system called Airtouch System, which improves user experience by remotely detecting single/multi-finger position. A single layer touch panel with triangular electrodes is used to achieve 3D multi-touch detection capability as well as manufacturing cost reduction. A lumped model of the touch panel is proposed to model the touch panel property and define the system specification. The hardware part of the proposed 3D touch sensor uses correlated double sampling (CDS) to achieve a high sensing resolution in Z direction and employs bootstrapping circuitry to reduce the mobile screen’s inter-channel-coupling effects. Additionally, to reduce chip area and assembly, the sensing oscillator is implemented with inverter-based active resonators instead of using either on or off chip inductors. The prototyped 3D touch sensor is fabricated using 65-nm CMOS process technology and consumes an area of 2mm2.

To detect the finger position in space, a new algorithm for finger position estimation is created with grouping filter invented to reduce system background noise. The algorithm is proposed to eliminate the fringing capacitance effect and achieve accurate finger position estimation. EM simulation proved that by taking account of fringing capacitance effect, the proposed algorithm reduced the systematic error by 11dB in the horizontal position detection. Accurate Z direction detection is achieved through using 2nd order polynomial curve to fit the EM model and compensate the non-linear fringing capacitance effect. The proposed system’s hardware circuit consumes 2.3mW and is fully compatible with existing mobile device environments. A prototype is built to demonstrate that the system can successfully detect finger movement in a vertical direction up to 6cm and achieve a horizontal resolution up to 0.6cm at 1cm finger-height. As a new interface for human and machine interactions, this system offers great potential in 3D gesture recognition for small-sized electronics and advanced human interactive games for mobile devices.

With the data rate of peripheral serial I/O for PCs and mobile computing platforms continuing to scale to meet high-bandwidth applications, the conventional serial interfaces are more than more challenging to achieve high bandwidth (>10Gb/s per lane), high energy efficiency (<10pJ/bit) and low cost, especially on complicated channel conditions, such as multi-drop buses and low-cost connectors/cables.

Conventional equalization solutions are very power-hungry and there is no universal solution capable of handling all different channel conditions. In the dissertation, a multi-band signaling with channel response learning mechanism will be introduced and a cognitive serial interface system will be proposed. The cognitive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth.

A cognitive tri-band transmitter (TX) and receiver (RX) with a forwarded clock using multi-band signaling and high-order digital signal modulations are designed, implemented and measured for serial link applications. The cognitive serial interface system features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at RX side, and then adapting modulation scheme, data bandwidth and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The proposed highly reconfigurable transceiver architecture is capable of dealing with low-cost serial channels, such as low-cost connectors, cables or multi-drop buses (MDB) with deep and narrow notches in the frequency domain (e.g., 40 dB loss at notches). The adaptive multi-band scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio (SNR) and channel bandwidth. The implemented cognitive serial interface prototype consumes 14.7 mW /15.2 mW power and occupies 0.016 /0.024 mm x mm on TX and RX side respectively. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy-efficient Figure of Merit (FoM) of 20.4 �W/Gb/s/dB for TX and 21.1 �W/Gb/s/dB, which is calculated based on power consumption of transmitting and receiving per Gb/s data and simultaneously overcoming per dB worst-case channel loss within the Nyquist frequency.

In the earlier days of the Complementary Metal Oxide Semiconductor (CMOS) industry, much effort was dedicated to the performance of device speed and number of transistors per processor core in response to Gordon Moore's law. However, the attention has gradually migrated to the system-level design, such as signaling and timing conventions for efficient data transactions. This is because the system clock speed is no longer limited by CMOS device cutoff frequencies, and the system performance becomes limited by either on- or off-chip interconnects. In order to overcome such difficulties, various ideas have been proposed including pre-distortion, equalization, and multi-level signaling. However, the burden on transferring data becomes dominant in overall system design as the demands for higher computing capabilities ever increase. My research focuses on maximizing the bandwidth efficiency by exploiting RF/Wireless techniques and minimizes the interconnect complexity. I explored 3 different hypotheses.

The first case is an on- and off-chip communication through copper wires. When a point-to-point or point-to-multi-point communication is established, the data signal experiences discontinuities through vias and connectors. Then, it affects the channel frequency response with deep notches where the signal undergoes resonances. A typical solution would equalize the channel based on the worst case notch, but the penalty is the reduced signal to noise ratio (SNR). Instead of sacrificing SNR, I accept the channel impairments and send data where there is no such notches using RF modulation on top of baseband signal.

The second case is a short-range wireless data communication through the air. Data connectors are everywhere in our daily lives. For instance, USB connectors in computers and cell phones, HDMI connectors in monitors and TVs. The mechanical parts are not only expensive but also bulky in size. Just as in first case, the high speed signal suffers discontinuities as well. Instead of struggling with mechanical parts, the wireless interconnect utilizes the abundant free-license band at 60GHz and provides giga-bits-per second (Gb/s) data rate with a minimum complexity and power efficiency because of its nature in short-range communication.

The last one is a mid-range (1meter to 10meter) data communication through plastic cables. In an example of data server communication market, the fiber optics has been a dominant solution because of the long-distance capability and large data bandwidth. However, it requires electrical to optical, and optical to electrical conversion with a strict temperature control. Keeping the advantage of low-loss channel characteristic, modulated RF signals can propagate through plastic tubes or strips without the cost of conversion process.

A technique to achieve ultra-wideband continuous frequency generation is introduced. It is based on orthogonal E-wall and H-wall tuning of distributed resonators, in standing wave mode configurations. The tuning scheme in fact serves dual purposes for generating concurrent tones as well as wide-band tuning operation. It is scalable and could be applied to any frequency band, but since it is designed around distributed resonators, it is more desirable for higher frequencies. In comparison with alternative methods, the technique requires less silicon space, lower power consumption, better phase noise, as well as a wider tuning range.