The ongoing exponential mobile traffic increase is continuing to push the requirements of wireless communication systems. Currently in dense urban areas the major limitation to the capacity of wireless links is interference between different users. Massive MIMO is a promising technology to address this challenge, where directional spatial beams are formed by an antenna array on a base station, each serving a different user. This concept is currently verified using commercial general-purpose analog hardware, with power consumption in the kW range for large arrays.

This thesis focuses on energy-efficient RF receiver design for Massive MIMO systems. In order to be energy-efficient, the system requirements for a large antenna array receiver are different from a conventional single-antenna receiver. We use the fact that the noise of each receiver is uncorrelated across the array, so we can save power by using receivers with larger noise, while still meeting the link budget requirements. However, receiver linearity cannot be relaxed due to the digital beamforming used in the system.

To address these challenges a novel RF receiver architecture is proposed, using a mixer-first approach with mixer switch resistance larger than 50 Ohm. Configurable mixer and baseband Gm sizes allow the receiver to trade noise figure for power consumption and use the same receiver for various array sizes and array-level noise specifications. Harmonic recombination is performed early in the signal path, enabling rejection of harmonic blockers up to -10dBm of power.

This architecture was implemented in a first chip prototype. Scalable element noise figure results in sub-2.5 dB array-level noise figure with 16 to 64 antennas and <368 mW total power consumption, for a frequency range of 0.25-1.7GHz.

In the second chip we perform an optimized design using the Berkeley Analog Generator (BAG). The proposed generator design methodology produces instances with optimum power consumption for a given noise figure specification. An instance of this generator is implemented in the chip, showing power consumption improvement of 50% and wider frequency range of 1-6GHz compared to the first chip.

Analog-to-Digital Converters (ADCs) serve as the interfaces between the analog natural world and the binary world of computer data. Due to this essential role, ADC circuits have been well studied over 40 years, and many problems associated with them have already been solved. However in recent years, a new species of ADCs has appeared, and since then attracted lots of attention. These are ultra-high-speed (often greater than 40GS/s) time-interleaved ADCs of low or medium resolution (around 6 to 8 bit) built in CMOS processes. Although such ADCs can be used in high-speed electronic measurement equipment and radar systems, the recent driving force behind them is next generation 100Gbps/400Gbps fiber optical transceivers. These transceivers take advantage of ultra-high-speed ADCs and digital-signal-processors (DSPs) to enable ultra-high data-rate communications in long-haul networks (city-to-city, transcontinental, and transoceanic fiber links), metro networks (fibers that connect enterprises in metropolitan areas), and data centers (fiber links within data center infrastructures). At such high sampling rate, massively time-interleaved successive-approximation ADC (SAR ADC) architecture has emerged as the dominant solution due to its excellent power efficiency. Several recent works has demonstrated success in achieving high sampling rate. However, the sampling network has become the bottleneck that limits the input bandwidth in these ADCs. It is apparent that conventional switch-based track-and-hold (T&H) circuit cannot satisfy the >20GHz bandwidth requirement. In addition, it is unclear what the optimal interleaving configuration is. Each state-of-the-art design adopts a different interleaving configuration – from straightforward conventional 1-rank interleaving to 2-rank hierarchical sampling or even 3 ranks. How to partition interleaving factors among different ranks has not yet been investigated. Furthermore, asynchronous SAR sub-ADCs are often used in these designs to push the sampling rate even further. The well-known sparkle-code issues caused by comparator meta-stability in asynchronous SARs can significantly increase the Bit-Error-Rate (BER) of the transceivers unless power hungry error correction coding are implemented in the system. Although many works in the literature attempted to deal with the meta-stability in asynchronous SARs, the effectiveness of these approaches have not been fully demonstrated. In this thesis, I will first propose a new cascode-based T&H circuits to improve the ADC bandwidth beyond the limit of conventional switch-based T&H circuits. Then, a system design and optimization methodology of hierarchical time-interleaved sampling network is presented in the context of cascode T&H. To deal with sparkle-code issue in asynchronous SAR sub-ADCs, a new back-end meta-stability correction technique is employed. An extensive statistical analysis is provided to verify the correction algorithm can greatly reduce sparkle-code error-rates. To further demonstrate the effectiveness of the proposed circuits and techniques, two prototype ADCs have been implemented. The first 7b 12.5GS/s hierarchically time-interleaved ADC in 65nm CMOS process demonstrates 29.4dB SNDR and >25GHz bandwidth. The later 6b 46GS/s ADC in 28nm CMOS employs asynchronous SAR sub-ADC design with back-end meta-stability correction. The measurement results show it achieves sparkle-code error free operation over 1e10 samples in addition to achieving >23GHz bandwidth and 25.2dB SNDR. The power consumption is 381mW from 1.05V/1.6V supplies, and the FOM is 0.56pJ/conversion-step.

The explosive development of various computation and communication platforms has demanded the per-pin I/O bandwidth of wireline links to increase at a commensurate rate, with projections to reach 60+Gb/s in less than 10 years. However, unlike the data-rate requirement, the power consumption of these links cannot increase, making improvements in the energy-efficiency of high-speed architectures and circuits crucial. In particular, equalization circuits such as feed-forward equalizers (FFE) and decision-feedback equalizers (DFE) are faced with the burden of compensating higher channel losses while running at faster speeds - all without allowing any increase in power consumption.

To address these challenges, this thesis first presents a feed-forward equalizing transmitter that utilizes voltage-mode signaling along with a shunting branch technique to improve signaling power. Due to the linear mapping between the equalization strength and output impedance segmentation from this technique, the associated decoding logic can be greatly simplified, and, thus, digital power overhead can be substantially reduced. Regulator-based impedance tracking loops are utilized to reduce the parasitics on the high-speed digital path to further reduce the digital power. A 2-tap prototype based on this architecture was taped out in Fujitsu 65nm LP CMOS process and achieves an overall of efficiency of 1pJ/b when operating at 10Gb/s with 200mV differential output signal amplitude.

To enable energy-efficient DFEs at even higher speeds, this thesis will then describe means to reduce the latency of the circuits within the intrinsic feedback loop of such equalizers. Specifically, techniques such as merged latch and summer, optimized signaling swing, and dynamic latches are combined to enable a multi-tap closed-loop DFE architecture that is capable of running at 60+Gb/s. A 3-tap prototype chip was fabricated in TSMC 65nm GP CMOS process, achieving ~0.7pJ/b at 66Gb/s when cancelling a total inter-symbol interference of ~1.65x of the cursor amplitude. This design represents by far the fastest DFE demonstrated to date with energy efficiency of better than 1pJ/bit, and highlights that the adoption of such techniques may pave the way forward for continued electrical I/O data-rate scaling.

After the introduction of these equalization circuits, this thesis will present a holistic link evaluation framework that aims to achieve more accurate power and performance estimation of link architectures at the beginning of a link design phase. With a compact circuit modeling methodology, circuit power and noise can be explicitly expressed in terms of both technology and system parameters (e.g. equalization-related parameters) such that a link's overall power and bit-error-rate can be directly estimated. An evaluation example shows that using TSMC 65nm GP CMOS process, it is possible to achieve a 64Gb/s data communication speed over a 1m long coax cable-based platform, which aligns with the previous DFE experimental results and thus proves the potentials of using this framework to guide the continued wireline data-rate scaling.

The continual expansion of Internet connectivity has raised data traffic substantially, increasing demands on high-bandwidth wireline communication systems. In contrast to the rapid increase in bandwidth that will be necessary, the allowable power consumption of high-speed transceivers remains relatively constant. Specifically, assuming the same total power budget as current designs, transceivers operating in the range of 50-60Gb/s must achieve 3-5pJ/bit efficiency to remain within the current total power window.

To address these trends and challenges, this thesis first reports a 60Gb/s receiver frontend in a 65nm CMOS process. Current integration combined with a cascode gate-voltage bias technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. The addition of interleaved, offset-canceled deserializing samplers addresses the high gain requirement of adaptive error-samplers. The prototype 65nm CMOS receiver operates at 60Gb/s, consuming 173mW from 1.2V and 1.0V supplies.

To enhance the productivity and quality of the receive equalizer design by capturing the parasitic loading and wiring capacitance promptly and precisely, an automated flow that generates the equalizer schematic and layout from target specifications and technology parameters is developed. Utilizing the Berkeley Analog Generator, the equalizer generation flow is scripted, executed, and iterated automatically to produce an optimal design that meets for a given configuration.

In addition to presenting the equalizer design, the thesis also introduces a new baud-rate CDR scheme that leverages the current integration frontend and phase dithering. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset. The resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The implemented 65nm CMOS transceiver operates at 60Gb/s with an eye-opening of 30% UI and consumes 288mW while equalizing 21dB of loss at 30GHz over a 0.7m Twinax cable.

Recent advances in wireless technologies have enabled fast increase of mobile data traffic. In fact, mobile data traffic has grown 18-fold over the past 5 years. The rapid growing demand imposes a big near-far problem on our wireless network. Beamforming technique provides an opportunity to efficiently solve the near-far problem, by combining elements in an antenna array in such a way that signals at particular angles experience constructive interference while others experience destructive interference.

This thesis focuses on the design of energy-efficient RF transmitters for large antenna array applications. In order to be energy-efficient, we should minimize the overhead power consumption. It makes the design challenging while minimizing out-of-band emissions and supporting multiple/reconfigurable bands as well as programmability in terms of performance (i.e., output power, noise figure, resolution, bandwidth, etc.), since any fixed frequency bandpass filters should be eliminated.

To address these challenges, a mixer-last TX architecture is proposed, which uses current DACs to deliver charge directly to the 50 Ohm output RF load. Out-of-band emissions are reduced by digital oversampling, and the charging operation of a baseband capacitor.

Using the proposed transmitter architectures, two chips were implemented. The first chip was fabricated in TSMC's 65nm CMOS technology. With a peak output power of 5.1dBm, the first chip consumes 49.2 mW and the measured noise floor at 40MHz offset is -155dBc/Hz. Realizing it is impossible to build a single transmitter that is power efficient under all applications, we developed a generator for our proposed TX architecture using Berkeley Analog Generator (BAG) framework. A generator captures the design methodology and is process portable. It could significantly lower the design cost so that different transmitters that are efficient for different design specifications can be generated.The second chip was generated by the generator and was fabricated in TSMC's 16nm CMOS technology. It consumes 5.14 mW at peak output power of -19.6 dBm. Compared with the first 65nm prototype, it is more power efficient in the output power range of less than -4 dBm.

The ever-increasing demand for ultra-high-speed interconnects has driven the development of wireline transceivers operating at >100Gbps per lane. As a major contribution of data random jitter, clock-dependant distortion of transmitters and receivers, the clock generation and distribution circuits in SerDes becomes increasingly complex and time-consuming with stringent specifications, especially considering the fast development of technology nodes of the FinFET processes. This thesis focuses on the design of energy-efficient clock generation and distribution network with generator-based design methodology using Berkeley Analog Generator, which speeds up the design procedure, while satisfying the performance requirements.

A bang-bang phase-locked loop generator for 28/32Gbps SerDes that encapsulates this design methodologies for its circuit blocks and the complete PLL system is first reported. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The rapid generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.

Furthermore, a flexible clock distribution network for a 200Gbps pulse amplitude modulation four-level transmitter is designed using the layout generators in 28nm CMOS technology. The proposed TX achieves an eye opening with >52.9mV eye height, 0.36UI eye width, >98% RLM and 4.63pJ/b at 200Gbps PAM-4 signaling under >6dB channel loss at 50GHz, demonstrating the highest data rate achieved using a planar process.

To complete the whole TX design, a layout generator for sub-100fs sub-sampling PLL is proposed. With a type-I loop and tri-state integral path, the voltage ripples of the hybrid loop is eliminated and the PLL reaches a RMS jitter of 44fs at 28GHz output, a spur of -56.6dB, which results in the FOM value -254.8dB. Finally, the PLL is merged with the transmitter data path, achieving 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under ~6dB channel loss at 50GHz, showing the capability of the generator-based design methodology.

Recent advance in wireless technologies has enabled rapid growth of mobile devices. Consequently, emerging applications for mobile devices have begun demanding data rates up to multiple Gb/s. Although advanced WiFi systems are approaching such data rates, the narrow bandwidth at ISM band fundamentally limits the achievable data-rate. Therefore, the unlicensed 7GHz of bandwidth at 60GHz band provides an opportunity to efficiently implement these communication systems with a potential to achieve $>$10Gb/s throughput. Besides the wider bandwidth, operating at higher frequency theoretically has higher achievable signal-to-noise ratio in area limited applications. This is because the maximum achievable antenna gain within limited aperture increases with frequency and it can be achieved using phased-array technique. This thesis therefore focuses on the design of 60GHz phased-array transceivers to support energy-efficient high data-rate communication systems.

Despite the advantages of 60GHz, mobile applications often require low power consumption as well as low cost implementation, making the design of 60GHz phased-array systems challenging. Taking into account the limited power budget, this research investigates the design choices of the number of elements in phased-array transceivers, and identifies that the overhead power is the bottleneck of energy efficiency. In order to reduce the overhead power in the transmitter, a new architecture using a fast start-up oscillator is proposed, which eliminates the need of explicit modulator and 60GHz LO delivery. Measurements has shown that the transmitter efficiency is boosted by more than 2X. More importantly, the overhead power is significantly reduced down to 2mW, making this architecture a good candidate for large number phased-array. On the other hand, suffering from the similar overhead problem, the receiver unfortunately could not share the same architecture. A different architecture that stacks the mixer on top of LO generation is thus proposed to reduce the power consumption in the receiver. This approach demonstrated a 2X power reduction in receiver overhead, and the resulted optimum number of receiver elements is close to 4.

Besides using CMOS technologies, on-chip antenna is also studied in order to further reduce the system cost. Slot-loop antenna is identified as a good candidate because that its intrinsic ground plane eases the integration with the rest of circuitry. Although the simulation shows an efficiency as high as $30\%$, the planar nature of the on-chip antenna limits its coverage in end-fire directions. Antenna diversity is thus proposed to overcome this limitation by utilizing multiple drive points on the same antenna. Because the antenna is fully integrated on-chip, antenna diversity can be implemented without extra high frequency I/Os, eliminating the loss that would be introduced otherwise.

Using the proposed transceiver architectures, a 4-element phased-array with on-chip antennas was fabricated on TSMC's 65nm CMOS technology as a test vehicle. Consuming 50mW in the transmitter and 65mW in the receiver, this 10.4Gb/s phased-array covers a range larger than 45cm in all directions. This achieves a state-of-art energy-efficiency of 11pJ/bit. The 29mW/element power consumption also demonstrates the lowest power of a single phased-array element.

A frequency-flexible radio-frequency (RF) front end has long been desired, but faces a myriad of obstacles to its realization. In recent years, the use of switching power amplifiers (PA) as part of digital PAs and RF digital-to-analog converters (RFDACs) has become more common. The primary motivation of these RFDACs is to directly convert from digital baseband bits to RF output. This is useful in the realization of a frequency-flexible RF front end, but this is prevented by the generation of significant spectral emissions in the form of harmonics and quantization noise by RFDACs. These issues are both typically remedied with the usage of high-order fixed filters which are inherently not frequency flexible.

In this dissertation, we will discuss an approach to implement a frequency-flexible digital PA-based transmitter using programmable integrated filtering to suppress spectral emissions without the use of external filters. Two filtering techniques will be discussed, as well as their requirements and limitations. Additionally, design automation of core blocks within the transmitters using the Berkeley Analog Generator (BAG) framework will be discussed in detail. We will demonstrate two prototypes implemented in 65nm and 28nm processes achieving state of the art filtering performance at a peak power level of > 23 dBm across at least a 1 GHz - 2 GHz frequency range.

Recent advances in the brain-machine interfaces (BMI) have demonstrated its clinical efficacy for various applications such as prosthetic controls for motor-disabled patients and neural disease treatments. Among many other signal modalities, electrophysiology is one of the key areas to understand and engineer neural system. While impressive technical breakthroughs on electrodes, signal acquisition, and microstimulation were made, no electrode-based instrumentation reported so far achieved both coverage and resolution required for a closed-loop BMI with a high-degree of freedom and a clinical lifespan.

In this dissertation, a minimally invasive neural interface system that has a scalability (starting from thousands of neural sites but targeting millions), a fine resolution (<10um, <1ms), a broad coverage (a year, >10cm), an automated electrode insertion, and a low-energy neuromodulation (<500uW for 64-channel recording). This system became feasible by integrating state-of-art sub-components developed across UC Berkeley and UCSF labs. Each subcomponent is reviewed along with discussions on current state-of-arts and challenges. Prototype in vitro and ex vivo results are also shown.

Another challenge for a bidirectional neural interface is existence of self-interference. While simultaneous stimulation and recording are required for neuromodulation chips to support closed-loop BMI applications, such ICs suffer from large stimulus artifacts. The stimulus artifact is essentially a self-interference that originates from a stimulator pulse and couples into front-end recorders. Because the ICs typically have front-ends with limited input ranges, they saturate and lose desired neural signals.

This dissertation presents an active cancellation IC that expands the effective dynamic range (uncancelled artifact/noise) of the front-end to 8kHz bandwidth and for up to 200mVpp differential-mode (DM) artifact signals with only a modest (~10%) noise penalty. The analog canceller with its LMS loop handles a majority of the artifact signal at the input of the LNA while the digital canceller with another LMS loop further cancels out residual error. The chip was validated with in vivo cancellation measurement result.

Complementary metal oxide semiconductor (CMOS) technology has a minimum energy per operation, and that limitation is one of the myriad hurdles CMOS faces as it reaches small scales. This minimum energy is set by the balance between leakage energy and dynamic energy in subthreshold CMOS circuits, and sets floors on the achievable energy of digital units. A new, post-CMOS device with a sharper subthreshold slope than CMOS would be able to sidestep this minimum energy constraint.

A candidate device called a nano-electromechancial (NEM) relay has recently emerged.

NEM relays are small, integrated, capacitively-actuated, mechanical switches. The devices have demonstrated extremely high subthreshold slopes: ten orders of magnitude over a millivolt of swing. However, in the same lithographic process they are twenty times larger than a minimum sized CMOS device, their gate capacitance is ten times that of a minimum sized CMOS device, and their mechanical motion is an order of magnitude slower than a CMOS inverter. Can NEM relays improve digital systems even with these drawbacks?

With proper circuit design, simulations say "yes". This dissertation examines three of the critical components of digital systems -- logic, timing, and memory -- and proposes NEM circuits which mitigate the weaknesses of the technology while achieving design goals. Simulations show that optimized relay logic, which arranges for all of the slow movement of relays to happen at the same time, can achieve an improvement of 10x in energy-per-operation below the CMOS minimum energy point at a penalty of 10x in delay and 3x in

area. This logic style is experimentally demonstrated. In addition, relay latch based timing with staticization in the feedback path is simulated, which results in a working relay pipeline with zero mechanical delays of timing overhead. Finally, a new device called NEMory is proposed to build dense, non-volatile, mechanical memory. A hybrid NEMory/CMOS array is simulated, and its performance is compared to other memory solutions. The NEMory density is higher than any non-volatile memory except for multi-level cell, o-chip Flash, and its read and write energy are lower than any other non-volatile technology. Finally, the scaling and process limits of realizing mechanical devices are discussed in the context of future work.