While being frequency compact and easy to implement, Non-Return to Zero (NRZ) encoded

data does not contain any energy at its clock frequency which makes the clock extraction

impossible using any kind of Linear Time Invariant (LTI) operations. Therefore, Clock Data

Recovery circuits (CDRs) have an inherent non linear recovery process. In this work we

present a frequency domain analysis of the mechanisms leading to the energy generation at clock frequency for NRZ clock data recovery systems. We also propose a frequency domain analysis which is applicable to both Bang-Bang and linear loops. We show the theory results match the measurements very well.

The operation of the voltage-mode and current-mode sense amplifiers (VSA and CSA) is explained in detail. Analytical expressions for offset arising from random FET mismatch are derived. The mechanism of two offset reduction method for VSA is explained. The supply-dependent offset for CSA is shown. The offset combined with signal attenuation define a figure-of-merit. The current-mode sense amplifier is shown to be superior at VDD < 0.6 ~ 0.7V.

Frequency-division duplexing (FDD) radios are widely used in wireless communication standards and multi-radio coexistence. It requires that the duplexer prevent both TX signal and noise from entering the receiver front-end, while operating under full TX power. It also requires the receiver front-end circuits to be highly linear when the TX leakage channel is adjacent to the receive channel.This work describes the design of a dual-band electrical balance duplexer (EBD). The electrical balance duplexer supports dual-band TX-RX isolation for FDD operation at 5-7GHz. A network in the EBD can balance the antenna impedance (ZANT) in the TX channel and RX channel independently. The EBD provides >40dB isolation in an 80MHz channel bandwidth in the TX band (5-6GHz), for any ZANT(fTX) with VSWR≤2, and independently in the RX band (6-7GHz) when QANT≤4.3. The EBD is designed for ≤4dB RX IL and ≤3.8dB TX IL. Second, the properties of finite-Q LCR networks are derived. Simple results and derivations provide performance limits and design guidelines for the on-chip filter (two-port) and impedance synthesizer (one-port). General properties are given for the design of multi-band on-chip N-port LCR networks. Third, second-order baseband filter circuits for mixer-first receivers are designed for adjacent channel blocker tolerance. The design guidelines are given in simple expressions. The independent poles control by circuit elements is achieved. The prototype measurements verify the design. It can tolerate the maximum TX leakage from the dual-band EBD without gain compression and noise degradation. Finally, the mixer switch nonlinearity is analyzed. Expressions for IIP3 and B1dB are given, showing the impact of supply voltage, FET size, clock waveform, operating frequency and baseband load. The analysis matches the simulation very well. The dual-band EBD and the mixer-first receiver with second-order baseband filters are fabricated in 65nm RF-SOI CMOS technology. They support the FDD operation for Wi-Fi 6/6E application between 5-7GHz.

Cognitive radios (CRs) use “white spaces” in spectrum for communication. This requires front-end circuits that are highly linear when the white space is adjacent to a strong blocker. For example, in the TV spectrum (54 MHz-862 MHz) broadcast transmissions are the blockers.

This work describes the design of a wideband blocker tolerant receiver. First EKV based MOSFET model is used to analyze RF transconductor distortion. Expressions for its IIP3 and P1dB are also given. Derivative superposition based linearization scheme for the RF transconductor is also explained.

Second mixer switch nonlinearity is analyzed using EKV. Simple expressions for receiver IIP3 and P1dB are given that provide design insights for linearity optimization. Low phase noise LO design is also described to lower receiver noise figure in the presence of large blockers.

Finally, transimpedance amplifier (TIA) large-signal operation is studied using EKV. It is shown that source follower inverter-based TIA transconductor results in higher receiver P1dB.

A prototype receiver based on these ideas was designed in 16nm FinFET CMOS. Measured results show that receiver can operate from 100 MHz to 6 GHz and it can tolerate up to +12 dBm blockers. Furthermore, its noise figure is only 8.9 dB in the presence of +10 dBm blocker located at 80 MHz offset.

In a wide-band RF system, the RF channel is located within 50 MHz to 9 GHz. A high-frequency resolution phase-locked loop (PLL) with 100$\%$ tuning range oscillator is the core to generate the RF carrier frequency which covers such a wide range. The phase noise and spurs of the PLL are required to be low to avoid degrading RF system performance. A PLL applies $\Sigma \Delta$ modulation to increases its resolution and is known as a fractional-N PLL, but $\Sigma \Delta$ modulation introduces considerable quantization noise into the loop. The nonlinearity of the PLL also converts part of the noise into fractional-N spurs. Noise cancellation is usually applied to eliminate this quantization noise. Calibration, often with long settling time, is necessary to maintain cancellation efficiency. Power intensive calibration is also required to notch spurious tones.

In this thesis, we first investigate the delay-locked loop (DLL) and attempt to use DLL to replace PLL as an RF frequency synthesizer. An LTI model of DLL is established, which indicates the limitation of DLL as a high-performance synthesizer. Then, the thesis focuses on PLL again. A calibration-free triple-loop PLL is introduced. The merits of heterodyne PLL are rediscovered, which applies a mixer in the loop to translate the VCO frequency to a low-frequency feedback signal. By implementing the harmonic mixing concept, the designed prototype effectively reduces the pulling risk of a traditional heterodyne PLL, allowing it to be integrated on a single chip. This PLL provides higher-order noise filtering and can naturally reduce fractional-N PLL noise and spurs. An analytical model for this PLL is also presented, which allows us to fully appreciate this PLL and optimize the loop design. After this, a sub-sampling PLL-based low-noise frequency extender is introduced, which increases the tuning range of an oscillator from 30$\%$ to 100$\%$, and requires only a small chip area. By combining the triple-loop PLL and the frequency extender, a synthesizer which can support a wideband radio system is achieved.

This thesis presents a comprehensive theory of wireless power transfer via inductive links. Design-oriented analysis is used to offer a different and insightful perspective. This thesis analyzes different architectures of wireless power transfer and different ways to realize stable power delivery over distance variations. Among various techniques for maintaining stable power delivery, a frequency-adapting architecture is proposed and implemented, in which an oscillator is used as the driver as compared with the traditional implementation of using power amplifier as the driver. The experimental results indicate that oscillator driven wireless power transfer system could self-tune to the optimal frequency and maintain stable power delivery over distance variation at a high power transfer efficiency.

The models of CMOS RF inductors are reviewed and improved for design. A compact frequency-independent equivalent circuit is developed for symmetric inductors used in VCOs. The equivalent circuit captures three basic parasitic effects, current crowding, substrate loss, and distributed capacity. All values of LCRM originate from the inductor geometry with a minimum number of fitting parameters.

Simple optimizations are attempted for maximum Q at the operating frequency. Three representative inductors are analyzed using the equivalent circuit. Good agreements have been obtained between the measurement result and the model. The optimization processes prove the optimality of the three sample inductors.

In this work, a general theory of coupled resonators is proposed. On one hand, it provides a design-oriented analysis while also preserving rigorousness throughout the derivation; on the other hand, it uses graphical methods to offer an intuitive understanding. Using an impedance loci analysis, it then ties the above to aspects together to render an integrated body of theory.

Guided by the developed theory, a robust wireless power transfer system using an oscillator driver is designed, capable of providing more than 90mW of power to a brain implant. Its maximum operating range spans 4.2cm and handles up to 40x load variations. It achieves a peak efficiency of more than 80%.

Building upon this wireless power system, a novel data modulation, Load-Induced Resonance-Shift Keying (L-RSK) is implemented to transmit reverse data simultaneously with the forward regulated power, at high rate and low power, through the same pair of coils. It can support up to 5Mb/s data rate and burns negligible power (at most 0.395mW) compared with the total delivered amount.

The milli-Watt level wireless power for biomedical implants can be extended to Watt level so that it can be used for charging portable consumer electronics. The scaled system can provide up to 11W power with 85% peak efficiency.

Lastly, second harmonics in LC oscillators are analyzed. Analysis on the second harmonics at the output and at the tail current source of current-mode LC oscillators provides useful insights on how to improve power-conversion efficiency. Anslysis on the second harmonics in oscillators with mismatch in threshold voltages of FETs shows that flicker noise at switching FETs of an LC oscillator can be up-converted to become phase noise at the output of the oscillation.

Envelope tracking is widely used to raise the efficiency of PAs. An envelope tracking supply modulator (ETSM) modulates PA's supply voltage to tracks the RF waveform's envelope, so that the PA will operate in saturation all the time. A hybrid amplifier is commonly used to realize the ETSM, which, in effect, partitions the envelope bandwidth into a low and high subband. An efficient switching buck converter tracks the low band. In parallel with it, an op-amp supplies the current in the high band. In prior arts, the hybrid amplifier is realized with feedback using a hysteresis comparator, whose output actuates the buck converter to respond to the changing envelope; the continuous-time op-amp makes up for the error. But a comparator-driven buck converter produces a slew-rate limited current that always lags the envelope waveform. This forces the op-amp to produce a larger current to correct the error, and the arrangement cannot guarantee that the buck converter switches no often than is absolutely necessary. We replace the hysteresis comparator with a novel trellis-search that, first, finds the optimal sequence to switch the buck converter to minimize the RMS current that the op-amp must deliver; second, to lower the loss from switching the capacitance of FETs, it penalizes a large number of switching events in the buck converter. Meanwhile, with a conventional on-chip hysteresis comparator, we can demonstrate ETSM operation up to 160 MHz modulation bandwidth. This is the widest bandwidth reported so far for any ETSM.

We define the nonlinear dynamic phenomenon of AM to PM distortion and discuss different candidate mechanisms. Qualitative descriptions of this from of distortion are turned into expressions, and are applied to FET RF power amplifier described in the literature. Most importantly, we are able to identify the dominant mechanism of AM-PM distortion in various practical circuits, which then suggests methods of remediation. Our theory is shown to match simulations and measurements.